AT89LP6440 datasheet(77/194 Pages) ATMEL

77 / 194 page

3706A–MICRO–9/09

AT89LP6440 - Preliminary

13.4.1

Asymmetrical PWM

For Asymmetrical PWM, Timer 2 should be configured for Auto-Reload mode and Count Mode 1

(CP/RL2 =0, DCEN = 0, T2CM1-0 = 01B). Asymmetrical PWM uses single slope operation as

shown in Figure 13-8. The timer counts up from BOTTOM to TOP and then restarts from BOT-

TOM. In non-inverting mode, the output CCx is set on the compare match between Timer 2

(TL2, TH2) and the channel data register (CCxL, CCxH), and cleared at BOTTOM. In inverting

mode, the output CCx is cleared on the compare match between Timer 2 and the data register,

and set at BOTTOM. The resulting asymmetrical output waveform is left-edge aligned.

The TOP value in RCAP2L and RCAP2H is double buffered such that the output frequency is

only updated at the TOP to BOTTOM overflow. The channel data register (CCxL, CCxH) is also

double-buffered such that the duty cycle is only updated at the TOP to BOTTOM overflow to pre-

vent glitches. The output frequency and duty cycle for asymmetrical PWM are given by the

following equations:

The extreme compare values represent special cases when generating a PWM waveform. If the

compare value is set equal to (or greater than) TOP, the output will remain low or high for non-

inverting and inverting modes, respectively. If the compare value is set to BOTTOM (0000H), the

output will remain high or low for non-inverting and inverting modes, respectively.

Figure 13-8. Asymmetrical (Edge-Aligned) PWM

13.4.2

Symmetrical PWM

For Symmetrical PWM, Timer 2 should be configured for Auto-Reload mode and Count Mode 2

or 3 (CP/RL2 = 0, DCEN = 0, T2CM1-0 =1xB). Symmetrical PWM uses dual-slope operation as

shown in Figure 13-9. The timer counts up from MIN to TOP and then counts down from TOP to

MIN. The timer is equal to TOP for exactly one clock cycle. In non-inverting mode, the output

CCx is cleared on the up-count compare match between Timer 2 (TL2, TH2) and the channel

data register (CCxL, CCxH), and set at the down-count compare match. In inverting mode, the

output CCx is set on the up-count compare match between Timer 2 and the data register, and

cleared at the down-count compare match. The resulting symmetrical PWM output waveform is

OUT

Oscillator Frequency

RCAP2H RCAP2L

}

----------------------------------------------------------------

TPS

---------------------

Inverting:

Duty Cycle

100%

CCxH CCxL

}

RCAP2H RCAP2L

}

----------------------------------------------------------------

Non-Inverting:

Duty Cycle

100%

RCAP2H RCAP2L

}

CCxH CCxL

}

–

RCAP2H RCAP2L

}

-------------------------------------------------------------------------------------------------------------

{RCAP2H,RCA2L}

CP/RL2 = 0, T2CM1-0 = 01B, DCEN = 0

Inverted

{CCxH,CCxL}

Non-inverted

CCx

AT89LP6440 bảng dữ liệu(PDF) 77 Page - ATMEL Corporation

AT89LP6440 bảng dữ liệu(HTML) 77 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL