AT89LP6440 datasheet(35/194 Pages) ATMEL

35 / 194 page

3706A–MICRO–9/09

AT89LP6440 - Preliminary

Note:

During a power-up sequence, the fuse selection is always overridden and therefore the pin will

always function as a reset input. An external circuit connected to this pin should not hold this

pin LOW during a power-on sequence if the pin will be configured as a general I/O, as this

will keep the device in reset until the pin transitions high. After the power-up delay, this input

will function either as an external reset input or as a digital input as defined by the fuse bit. Only a

power-up reset will temporarily override the selection defined by the reset fuse bit. Other sources

of reset will not override the reset fuse bit. P4.2/RST also serves as the In-System Programming

(ISP) enable. ISP is enabled when the external reset pin is held low. When the reset pin is dis-

abled by the fuse, ISP may only be entered by pulling P4.2 low during power-up.

7.4

Watchdog Reset

When the Watchdog times out, it will generate an internal reset pulse lasting 16 clock cycles.

Watchdog reset will also set the WDTOVF flag in WDTCON. To prevent a Watchdog reset, the

watchdog reset sequence 1EH/E1H must be written to WDTRST before the Watchdog times

out. See “Programmable Watchdog Timer” on page 141. for details on the operation of the

Watchdog.

7.5

Software Reset

The CPU may generate an internal 16-clock cycle reset pulse by writing the software reset

sequence 5AH/A5H to the WDRST register. A software reset will set the SWRST bit in WDT-

CON. See “Software Reset” on page 142 for more information on software reset. Writing any

sequences other than 5AH/A5H or 1EH/E1H to WDTRST will generate an immediate reset and

set both WDTOVF and SWRST to flag an error.

Power Saving Modes

The AT89LP6440 supports two different power-reducing modes: Idle and Power-down. These

modes are accessed through the PCON register. Additional steps may be required to achieve

the lowest possible power consumption while using these modes.

8.1

Idle Mode

Setting the IDL bit in PCON enters idle mode. Idle mode halts the internal CPU clock. The CPU

state is preserved in its entirety, including the RAM, stack pointer, program counter, program

status word, and accumulator. The Port pins hold the logic states they had at the time that Idle

was activated. Idle mode leaves the peripherals running in order to allow them to wake up the

CPU when an interrupt is generated. The timers, UART, SPI, TWI, comparators, ADC, GPI and

CCA peripherals continue to function during Idle. If these functions are not needed during idle,

they should be explicitly disabled by clearing the appropriate control bits in their respective

SFRs. The watchdog may be selectively enabled or disabled during Idle by setting/clearing the

WDIDLE bit. The Brown-out Detector, if enabled, is always active during Idle. Any enabled inter-

rupt source or reset may terminate Idle mode. When exiting Idle mode with an interrupt, the

interrupt will immediately be serviced, and following RETI the next instruction to be executed will

be the one following the instruction that put the device into Idle.

The power consumption during Idle mode can be further reduced by prescaling down the system

clock using the System Clock Divider (Section 6.5 on page 31). Be aware that the clock divider

will affect all peripheral functions except the ADC. Therefore baud rates or PWM periods may

need to be adjusted to maintain their rate with the new clock frequency.

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