AT89LP6440 datasheet(9/194 Pages) ATMEL

9 / 194 page

3706A–MICRO–9/09

AT89LP6440 - Preliminary

There is no difference in counting rate between Timer 2’s Auto-Reload/Capture and Baud

Rate/Clock Out modes. All modes increment the timer once per clock cycle. Timer 2 in Auto-

Reload/Capture mode increments at 12 times the rate of standard 8051s. Setting TPS

3-0 =

1101B will force Timer 2 to count every twelve clocks. Timer 2 in Baud Rate or Clock Out mode

increments at twice the rate of standard 8051s. Setting TPS

3-0 = 0001B will force Timer 2 to

count every two clocks.

2.2.6

Serial Port

The baud rate of the UART in Mode 0 defaults to 1/4 the clock frequency, compared to 1/12 the

clock frequency in the standard 8051. In should also be noted that when using Timer 1 to gener-

ate the baud rate in UART Modes 1 or 3, the timer counts at the clock frequency and not at 1/12

the clock frequency. To maintain the same baud rate in the AT89LP6440 while running at the

same frequency as a standard 8051, the time-out period must be 12 times longer. Mode 1 of

Timer 1 supports 16-bit auto-reload to facilitate longer time-out periods for generating low baud

rates.

Timer 2 generated baud rates are twice as fast in the AT89LP6440 than on standard 8051s

when operating at the same frequency. The Timer Prescaler can also scale the baud rate to

match an existing application.

2.2.7

SPI

The Serial Peripheral Interface (SPI) has a dedicated interrupt vector. The ESPI (IE2.2) bit

replaces SPIE (SPCR.7). SPCR.7 (TSCK) now enables timer-generated baud rate.

The SPI includes Mode Fault detection. If multiple-master capabilities are not required, SSIG

(SPSR.2) must be set to one for master mode to function correctly when SS (P1.4) is a general

purpose I/O.

2.2.8

Watchdog Timer

The Watchdog Timer in AT89LP6440 counts at a rate of once per clock cycle. This compares to

once every 12 clocks in the standard 8051. A common prescaler is available to divide the time

base for all timers and reduce the counting rate.

2.2.9

I/O Ports

The I/O ports of the AT89LP6440 may be configured in four different modes. By default all the

I/O ports revert to input-only (tristated) mode at power-up or reset. In the standard 8051, all ports

are weakly pulled high during power-up or reset. To enable 8051-like ports, the ports must be

put into quasi-bidirectional mode by clearing the P1M0, P2M0, P3M0 and P4M0 SFRs. The user

can also configure the ports to start in quasi-bidirectional mode by disabling the Tristate-Port

User Fuse. When this fuse is disabled, P1M0, P2M0, P3M0 and P4M0 will reset to 00h instead

of FFh and the ports will be weakly pulled high. Port 0 and the upper nibble of Port 2 always

power up tristated regardless of the fuse setting due to their analog functions.

2.2.10

External Memory Interface

The AT89LP6440 does not support external program memory. The PSEN and EA functions are

not supported and those pins are replaced with general purpose I/O. The ALE strobe does not

toggle continuously and cannot be used as a board-level clock.

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