AT89LP6440 datasheet(14/194 Pages) ATMEL

14 / 194 page

3706A–MICRO–9/09

AT89LP6440 - Preliminary

To enable write access to the nonvolatile data memory, the MWEN bit (MEMCON.4) must be set

to one. When MWEN = 1 and DMEN = 1, MOVX @DPTR,A may be used to write to FDATA.

FDATA uses flash memory with a page-based programming model. Flash data memory differs

from traditional EEPROM data memory in the method of writing data. EEPROM generally can

update a single byte with any value. Flash memory splits programming into write and erase

operations. A Flash write can only program zeroes, i.e change ones into zeroes (). Any

ones in the write data are ignored. A Flash erase sets an entire page of data to ones so that all

bytes become FFH. Therefore after an erase, each byte in the page can be written only once

with any possible value. Bytes can not be overwritten once they are changed from the erased

state without possibility of corrupting the data. Therefore, if even a single byte needs updating;

then the contents of the page must first be saved, the entire page must be erased and the zero

bits in all bytes (old and new data combined) must be written. Avoiding unnecessary page

erases greatly improves the endurance of the memory.

The AT89LP6440 includes 64 data pages of 128 bytes each. One or more bytes in a page may

be written at one time. The AT89LP6440 includes a temporary page buffer of 64 bytes, or half of

a page. Because the page buffer is 64 bytes long, the maximum number of bytes written at one

time is 64. Therefore, two write cycles are required to fill the entire 128-byte page, one for the

low half page (00H–3FH) and one for the high half page (40H–7FH) as shown in Figure 3-4.

Figure 3-4.

Page Programming Structure

The LDPG bit (MEMCON.5) allows multiple data bytes to be loaded to the temporary page buf-

fer. While LDPG = 1, MOVX @DPTR,A instructions will load data to the page buffer, but will not

start a write sequence. Note that a previously loaded byte must not be reloaded prior to the write

sequence. To write the half page into the memory, LDPG must first be cleared and then a

MOVX @DPTR,A with the final data byte is issued. The address of the final MOVX determines

which half page will be written. If a MOVX @DPTR,A instruction is issued while LDPG = 0 with-

out loading any previous bytes, only a single byte will be written. The page buffer is reset after

each write operation. Figures 3-5 and Figure 3-6 on page 15 show the difference between byte

writes and page writes.

Figure 3-5.

FDATA Byte Write

→

Low Half Page

Data Memory

High Half Page

Page Buffer

MWEN

DMEN

LDPG

IDLE

MOVX

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