AT89LP6440 datasheet(29/194 Pages) ATMEL

29 / 194 page

3706A–MICRO–9/09

AT89LP6440 - Preliminary

5.3

Instruction Set Extensions

Table 5-8 lists the additions to the 8051 instruction set that are supported by the AT89LP6440.

For more information on the instruction set see Section 22. “Instruction Set Summary” on page

143. For detailed descriptions of the extended instructions see Section 22.1 “Instruction Set

Extensions” on page 147.

• The /DPTR instructions provide support for the dual data pointer features described above

(See Section 5.2).

•The ASR M, LSL M, CLR M and MAC AB instructions are part of the Multiply-Accumulate

Unit (See Section 5.1).

•The JMP @A+PC instruction supports localized jump tables without using a data pointer.

•The CJNE A, @R

i, rel instructions allow compares of array values with non-constant values.

• The BREAK instruction is used by the On-Chip Debug system. See Section 24. on page 155.

Table 5-8.

AT89LP6440 Extended Instructions

Opcode

Mnemonic

Description

Bytes

Cycles

A5 00

BREAK

Software breakpoint

A5 03

ASR M

Arithmetic shift right of M register

A5 23

LSL M

Logical shift left of M register

A5 73

JMP @A+PC

Indirect jump relative to PC

A5 90

MOV /DPTR, #data16

Move 16-bit constant to alternate data

pointer

A5 93

MOVC A, @A+/DPTR

Move code location to ACC relative to

alternate data pointer

A5 A3

INC /DPTR

Increment alternate data pointer

A5 A4

MAC AB

Multiply and accumulate

A5 B6

CJNE A, @R0, rel

Compare ACC to indirect RAM and

jump if not equal

A5 B7

CJNE A, @R1, rel

Compare ACC to indirect RAM and

jump if not equal

A5 E0

MOVX A, @/DPTR

Move external to ACC; 16-bit address

in alternate data pointer

23/5

A5 E4

CLR M

Clear M register

A5 F0

MOVX @/DPTR, A

Move ACC to external; 16-bit address

in alternate data pointer

23/5

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