AT89LP6440 datasheet(34/194 Pages) ATMEL

34 / 194 page

3706A–MICRO–9/09

AT89LP6440 - Preliminary

meet the minimum system requirements before the device exits reset and starts normal opera-

tion. The RST pin may be held low externally until these conditions are met.

7.2

Brown-out Reset

The AT89LP6440 has an on-chip Brown-out Detection (BOD) circuit for monitoring the V

DD level

during operation by comparing it to a fixed trigger level. The trigger level V

BOD for the BOD is

nominally 2.0V. The purpose of the BOD is to ensure that if V

DD fails or dips while executing at

speed, the system will gracefully enter reset without the possibility of errors induced by incorrect

execution. A BOD sequence is shown in Figure 7-3. When V

DD decreases to a value below the

trigger level V

BOD, the internal reset is immediately activated. When VDD increases above the

trigger level plus about 200 mV of hysteresis, the start-up timer releases the internal reset after

the specified time-out period has expired (Table 7-1). The Brown-out Detector must be enabled

by setting the BOD Enable Fuse. (See “User Configuration Fuses” on page 164.)

Figure 7-3.

Brown-out Detector Reset

The AT89LP6440 allows for a wide V

DD operating range. The on-chip BOD may not be sufficient

to prevent incorrect execution if V

BOD is lower than the minimum required VDD range, such as

when a 3.6V supply is coupled with high frequency operation. In such cases an external Brown-

out Reset circuit connected to the RST pin may be required.

7.3

External Reset

The P4.2/RST pin can function as either an active-LOW reset input or as a digital general-

purpose I/O, P4.2. The Reset Pin Enable Fuse, when set to “1”, enables the external reset input

function on P4.2. (See “User Configuration Fuses” on page 164.) When cleared, P4.2 may be

used as an input or output pin. When configured as a reset input, the pin must be held low for at

least two clock cycles to trigger the internal reset. The RST pin includes an on-chip pull-up resis-

tor tied to V

DD. The pull-up is disabled when the pin is configured as P4.2.

Table 7-1.

Start-up Timer Settings

SUT Fuse 1

SUT Fuse 0

Clock Source

SUT (± 5%) µs

Internal RC/External Clock

Crystal Oscillator

1024

Internal RC/External Clock

512

Crystal Oscillator

2048

Internal RC/External Clock

1024

Crystal Oscillator

4096

Internal RC/External Clock

4096

Crystal Oscillator

16384

VDD

Time-out

VPOR

Internal

Reset

tSUT

VBOD

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