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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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AT89LP6440 bảng dữ liệu(PDF) 28 Page - ATMEL Corporation |
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AT89LP6440 bảng dữ liệu(HTML) 28 Page - ATMEL Corporation |
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28 / 194 page  28 3706A–MICRO–9/09 AT89LP6440 - Preliminary 5.2.2.2 Index Disable The MOVC Index Disable bit, MVCD (DSPR.1), disables the indexed addressing mode of the MOVC A, @A+DPTR instruction. When MVCD = 1, the MOVC instruction functions as MOVC A, @DPTR with no indexing as shown in Table 5-7. MVCD can improve the efficiency of routines that must fetch multiple operands from program memory. DPRB can change the MOVC destination register from ACC to B, but has no effect on the MOVC index register. 5.2.2.3 Circular Buffers The CBE0 and CBE1 bits in DSPR can configure DPTR0 and DPTR1, respectively, to operate in circular buffer mode. The AT89LP6440 maps circular buffers into two identically sized regions of EDATA/XDATA. These buffers can speed up convolution computations such as FIR and IAR digital filters. The length of the buffers are set by the value of the FIRD (E3H) register for up to 256 entries. Buffer A is mapped from 0000H to FIRD and Buffer B is mapped from 0100H to 100H+FIRD as shown in Figure 5-6. Both data pointers may operate in either buffer. When cir- cular buffer mode is enabled, updates to a data pointer referencing the buffer region will follow circular addressing rules. If the data pointer is equal to FIRD or 100H+FIRD any increment will cause it to overflow to 0000H or 0100H respectively. If the data pointer is equal to 0000H or 0100H any decrement will cause it to underflow to FIRD or 100H+FIRD respectively. In this mode, updates can be either an explicit INC DPTR or an automatic update using DPUn where the DPDn bits control the direction. The data pointer will increment or decrement normally at any other addresses. Therefore, when circular addressing is in use, the data pointers can still oper- ate as regular pointers in the FIRD+1 to 00FFH and greater than 100H+FIRD ranges. Figure 5-6. Circular Buffer Mode Table 5-7. MOVC @DPTR Operating Modes MVCD DPRB Equivalent Operation for MOVC A, @A+DPTR DPS = 0 DPS = 1 DPTR /DPTR DPTR /DPTR 00 MOVC A, @A+DPTR0 MOVC A, @A+DPTR1 MOVC A, @A+DPTR1 MOVC A, @A+DPTR0 01 MOVC A, @A+DPTR0 MOVC B, @A+DPTR1 MOVC B, @A+DPTR1 MOVC A, @A+DPTR0 10 MOVC A, @DPTR0 MOVC A, @DPTR1 MOVC A, @DPTR1 MOVC A, @DPTR0 11 MOVC A, @DPTR0 MOVC B, @DPTR1 MOVC B, @DPTR1 MOVC A, @DPTR0 0000h DPTR 0100h FIRD 100h + FIRD DPTR A B |
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