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PCIMX515CJM6C bảng dữ liệu(PDF) 123 Page - Freescale Semiconductor, Inc

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Giải thích chi tiết về linh kiện  i.MX51 Applications Processors for Consumer and Industrial Products
PDF  184 Pages
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PCIMX515CJM6C bảng dữ liệu(HTML) 123 Page - Freescale Semiconductor, Inc

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Electrical Characteristics
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1
Freescale Semiconductor
123
Preliminary—Subject to Change Without Notice
3.7.15.2
SSI Receiver Timing with Internal Clock
Figure 90. SSI Receiver Internal Clock Timing Diagram
Table 90. SSI Receiver Timing with Internal Clock
ID
Parameter
Min
Max
Unit
Internal Clock Operation
SS1
(Tx/Rx) CK clock period
81.4
—
ns
SS2
(Tx/Rx) CK clock high period
36.0
—
ns
SS3
(Tx/Rx) CK clock rise time
—
6.0
ns
SS4
(Tx/Rx) CK clock low period
36.0
—
ns
SS5
(Tx/Rx) CK clock fall time
—
6.0
ns
SS7
(Rx) CK high to FS (bl) high
—
15.0
ns
SS9
(Rx) CK high to FS (bl) low
—
15.0
ns
SS11
(Rx) CK high to FS (wl) high
—
15.0
ns
SS13
(Rx) CK high to FS (wl) low
—
15.0
ns
SS20
SRXD setup time before (Rx) CK low
10.0
—
ns
SS21
SRXD hold time after (Rx) CK low
0.0
—
ns
Oversampling Clock Operation
SS47
Oversampling clock period
15.04
—
ns
SS50
SS48
SS1
SS4
SS2
SS51
SS20
SS21
SS49
SS7
SS9
SS11
SS13
SS47
SS3
SS5
TXC
(Output)
TXFS (bl)
(Output)
TXFS (wl)
(Output)
RXD
(Input)
RXC
(Output)



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