PCIMX515CJM6C datasheet(47/184 Pages) FREESCALE

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Electrical Characteristics

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

3.6.7.4

Examples of WEIM Accesses

The following diagrams give few examples of basic WEIM accesses to external memory devices with the

timing parameters mentioned previously for specific control parameters settings.

Figure 20. Synchronous Memory Read Access, WSC=1

WE20

WAIT_B setup time to

Clock rise

2—

—

WE21

WAIT_B hold time from

Clock rise

2.5

—

2.5

—

2.5

—

2.5

—

1 t is axi_clk cycle time. The maximum allowed axi_clk frequency is 133 MHz, whereas the maximum allowed BCLK frequency

is 104 MHz. As a result if BCD = 0, axi_clk must be

≤104 MHz. If BCD = 1, then 133 MHz is allowed for axi_clk, resulting in

a BCLK of 66.5 MHz. When the clock branch to WEIM is decreased to 104 MHz, other busses are impacted which are

clocked from this source. See the CCM chapter of the i.MX51 Reference Manual for a detailed clock tree description.

2 BCLK parameters are being measured from the 50% point. i.e., high is defined as 50% of signal value and low is defined as

50% as signal value.

3 For signal measurements “High” is defined as 80% of signal value and “Low” is defined as 20% of signal value.

Table 40. WEIM Bus Timing Parameters (continued)1

Parameter

BCD = 0

BCD = 1

BCD = 2

BCD = 3

Min

Max

Min

Max

Min

Max

Min

Max

Last Valid Address

Address v1

D(v1)

BCLK

ADDR

DATA

WE_B

ADV_B

OE_B

BEy_B

CSx_B

Next Address

WE4

WE5

WE6

WE7

WE10

WE11

WE13

WE12

WE14

WE15

WE18

WE19

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