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PCIMX515CJM6C bảng dữ liệu(PDF) 62 Page - Freescale Semiconductor, Inc

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Giải thích chi tiết về linh kiện  i.MX51 Applications Processors for Consumer and Industrial Products
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PCIMX515CJM6C bảng dữ liệu(HTML) 62 Page - Freescale Semiconductor, Inc

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i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1
62
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical Characteristics
3.7.1.2
CSPI Slave Mode Timing
Figure 36 depicts the timing of CSPI in Slave mode. Table 53 lists the CSPI Slave Mode timing
characteristics.
Figure 36. CSPI Slave Mode Timing Diagram
CS10
CSPIx_DI Hold Time
tHmiso
5—
ns
CS11
CSPIx_DRYN Setup Time
tSDRY
5—
ns
Table 53. CSPI Slave Mode Timing Parameters
ID
Parameter
Symbol
Min
Max
Unit
CS1
CSPIx_CLK Cycle Time
tclk
60
—
ns
CS2
CSPIx_CLK High or Low Time
tSW
15
—
ns
CS3
CSPIx_CLK Rise or Fall
tRISE/FALL
——
ns
CS4
CSPIx_CS_x pulse width
tCSLH
30
—
ns
CS5
CSPIx_CS_x Lead Time (CS setup time)
tSCS
5—
ns
CS6
CSPIx_CS_x Lag Time (CS hold time)
tHCS
5—
ns
CS7
CSPIx_DO Setup Time
tSmosi
5—
ns
CS8
CSPIx_DO Hold Time
tHmosi
5—
ns
CS9
CSPIx_DI Setup Time
tSmiso
5—
ns
CS10
CSPIx_DI Hold Time
tHmiso
5—
ns
Table 52. CSPI Master Mode Timing Parameters (continued)
ID
Parameter
Symbol
Min
Max
Unit
CS1
CS7 CS8
CS2
CS2
CS4
CS6
CS5
CS9 CS10
CSPIx_CLK
CSPIx_CS_x
CSPIx_DI
CSPIx_DO
CS3
CS3



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