PCIMX515CJM6C datasheet(69/184 Pages) FREESCALE

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Electrical Characteristics

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

Figure 43. MII Serial Management Channel Timing Diagram

3.7.5

Frequency Pre-Multiplier (FPM) Electrical Parameters (CKIL)

The FPM is a DPLL that converts a signal operating in the kilohertz region into a clock signal operating

in the megahertz region. The output of the FPM provides the reference frequency for the on-chip DPLLs.

Parameters of the FPM are listed in Table 61.

3.7.6

High-Speed I2C (HS-I2C) Timing Parameters

This section describes the timing parameters of the HS-I2C module. This module can operate in the

following modes: Standard, Fast and High speed.

NOTE

See the errata for the HS-I2C module in the i.MX51 Chip Errata. There are

two standard I2C modules that have no errata.

Table 61. FPM Specifications

Parameter

Min

Typ

Max

Unit

Reference clock frequency range—CKIL

32.768

256

kHz

FPM output clock frequency range

—

MHz

FPM multiplication factor (test condition is changed by a factor of 2)

128

—

1024

—

Lock-in time1

1 plrf = 1 cycle assumed missed + x cycles for reset deassert + y cycles for calibration and lock x[ts] = {2,3,5,9};

y[ts] = {7,8,10,14}; where ts is the chosen time scale of the reference clock. In this case reference clock = 32 kHz which makes

ts = 0, therefore total time required for achieving lock is 10(1+2+7) cycles or 312.5

µs.

—

312.5

µs

Cycle-to-cycle frequency jitter (peak to peak)

—

FEC_MDC (output)

FEC_MDIO (output)

M14

M15

M10

M11

M12

M13

FEC_MDIO (input)

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