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Giải thích chi tiết về linh kiện  i.MX51 Applications Processors for Consumer and Industrial Products
PDF  184 Pages
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PCIMX515CJM6C bảng dữ liệu(HTML) 93 Page - Freescale Semiconductor, Inc

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Electrical Characteristics
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1
Freescale Semiconductor
93
Preliminary—Subject to Change Without Notice
3.7.8.7.2
Asynchronous Parallel Interface Timing Parameters
Figure 60 depicts timing of asynchronous parallel interfaces based on the system 80 and system 68k
interfaces. Table 71 shows timing characteristics at display access level. All timing diagrams are based
on active low control signals (signals polarity is controlled via the DI_DISP_SIG_POL Register).
Figure 60. Asynchronous Parallel Interface Timing Diagram
Table 70. Asynchronous Display Interface Timing Parameters (Pixel Level)
ID
Parameter
Symbol
Value
Description
Unit
IP27
Read system cycle time
Tcycr
ACCESS_SIZE_#
predefined value in DI REGISTER
ns
IP28a
Address Write system cycle time Tcycwa
ACCESS_SIZE_#
predefined value in DI REGISTER
ns
IP28d
Data Write system cycle time
Tcycwd
ACCESS_SIZE_#
predefined value in DI REGISTER
ns
IP29
RS start
Tdcsrr
UP#
RS strobe switch, predefined value
in DI REGISTER
ns
IP30
CS start
Tdcsc
UP#
CS strobe switch, predefined value
in DI REGISTER
ns
IP31
CS hold
Tdchc
DOWN#
CS strobe release, predefined
value in DI REGISTER
—
DI clock
RS
WR
RD
A0
D0
D1
PP_DATA_IN
D2
D3
IP27
IP28d
IP28a
IP37
IP33
IP35
IP38
IP34
IP36
IP29
IP31
IP32
IP47
IP30
IPP_CS
IPP_DATA



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