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PCIMX515CJM6C bảng dữ liệu(PDF) 67 Page - Freescale Semiconductor, Inc

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Giải thích chi tiết về linh kiện  i.MX51 Applications Processors for Consumer and Industrial Products
PDF  184 Pages
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nhà sản xuất  FREESCALE [Freescale Semiconductor, Inc]
Trang chủ  http://www.freescale.com
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PCIMX515CJM6C bảng dữ liệu(HTML) 67 Page - Freescale Semiconductor, Inc

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Electrical Characteristics
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1
Freescale Semiconductor
67
Preliminary—Subject to Change Without Notice
Figure 40. MII Receive Signal Timing Diagram
3.7.4.2
MII Transmit Signal Timing
The MII transmit signal timing affects the FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER, and
FEC_TX_CLK signals. The transmitter functions correctly up to a FEC_TX_CLK maximum frequency
of 25 MHz + 1%. There is no minimum frequency requirement. In addition, the processor clock frequency
must exceed twice the FEC_TX_CLK frequency. Table 58 lists MII transmit channel timing parameters
and Figure 41 shows MII transmit signal timing diagram for the values listed in Table 58.
.
Figure 41. MII Transmit Signal Timing Diagram
Table 58. MII Transmit Signal Timing
Num
Characteristic1
1 FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing in 10 Mbps 7-wire interface mode.
Min
Max
Unit
M5
FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER invalid
5
—
ns
M6
FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER valid
—
20
ns
M7
FEC_TX_CLK pulse width high
35%
65%
FEC_TX_CLK period
M8
FEC_TX_CLK pulse width low
35%
65%
FEC_TX_CLK period
FEC_RX_CLK (input)
FEC_RXD[3:0] (inputs)
FEC_RX_DV
FEC_RX_ER
M3
M4
M1
M2
FEC_TX_CLK (input)
FEC_TXD[3:0] (outputs)
FEC_TX_EN
FEC_TX_ER
M7
M8
M5
M6



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