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Giải thích chi tiết về linh kiện  i.MX51 Applications Processors for Consumer and Industrial Products
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nhà sản xuất  FREESCALE [Freescale Semiconductor, Inc]
Trang chủ  http://www.freescale.com
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PCIMX515CJM6C bảng dữ liệu(HTML) 60 Page - Freescale Semiconductor, Inc

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i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1
60
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical Characteristics
Figure 34. DDR2 SDRAM DQ vs. DQS and SDCLK READ Cycle
3.7
External Peripheral Interfaces
3.7.1
CSPI Timing Parameters
This section describes the timing parameters of the CSPI. The CSPI has separate timing parameters for
master and slave modes. The nomenclature used with the CSPI modules and the respective routing of these
signals is shown in Table 51 on page 61.
Table 50. DDR2 SDRAM Read Cycle1
1 Test conditions are: Capacitance of 15 pF for DDR contacts. The recommended drive strength is Medium for SDCLK and High
for address and controls
ID
Parameter
Symbol
SDCLK = 200 MHz2
2 SDCLK and DQS related parameters are being measured from the 50% point. that is, high is defined as 50% of signal value
and low is defined as 50% as signal value. DDR SDRAM CLK parameters are measured at the crossing point of SDCLK and
SDCLK_B.
Unit
Min
Max
DDR24
DQS - DQ Skew (defines the Data valid window in read cycles related to
DQS).
tDQSQ
—0.35
ns
DDR25
DQS DQ in HOLD time from DQS
tQH
1.8
—
ns
DDR26
DQS output access time from SDCLK posedge
tDQSCK
–0.5
0.5
ns
SDCLK
SDCLK_B
DQS (input)
DQ (input)
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DDR26
DDR24
DDR25



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