PCIMX515CJM6C datasheet(105/184 Pages) FREESCALE

105 / 184 page

Electrical Characteristics

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1

Freescale Semiconductor

105

Preliminary—Subject to Change Without Notice

Figure 70. P-ATA Interface Signals Timing Diagram

The user needs to use level shifters for 5.0 V compatibility on the ATA interface. The i.MX51 P-ATA

interface is 3.3 V compatible.

The use of bus buffers introduces delay on the bus and introduces skew between signal lines. These factors

make it difficult to operate the bus at the highest speed (UDMA-5) when bus buffers are used. If fast

UDMA mode operation is needed, this may not be compatible with bus buffers.

Another area of attention is the slew rate limit imposed by the ATA specification on the ATA bus.

According to this limit, any signal driven on the bus should have a slew rate between 0.4 and 1.2 V/ns with

a 40 pF load. Not many vendors of bus buffers specify slew rate of the outgoing signals.

When bus buffers are used, the ata_data bus buffer is special. This is a bidirectional bus buffer, so a

direction control signal is needed. This direction control signal is ata_buffer_en. When its high, the bus

should drive from host to device. When its low, the bus should drive from device to host. Steering of the

signal is such that contention on the host and device tri-state busses is always avoided.

Table 77. AC Characteristics of All Interface Signals

Parameter

Symbol

Min

Max

Unit

SI1

Rising edge slew rate for any signal on ATA interface.1

1 SRISE and SFALL shall meet this requirement when measured at the sender’s connector from 10–90% of full signal

amplitude with all capacitive loads from 15

–40 pF where all signals have the same capacitive load value.

Srise

—

1.25

V/ns

SI2

Falling edge slew rate for any signal on ATA interface (see note)

Sfall

—

1.25

V/ns

SI3

Host interface signal capacitance at the host connector

Chost

—20

ATA Interface Signals

SI1

SI2

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