TLC320AD50CSLASHI datasheet(12/54 Pages) TI2

12 / 54 page

1–5

1.5

Terminal Functions (Continued)

TERMINAL

NAME

NO.

I/O

DESCRIPTION

M/S

Master/slave select input. When M/S is high, the device is the master. When M/S is low, the device is a slave.

MCLK

Master clock. MCLK derives the internal clocks of the sigma-delta analog interface circuit.

MONOUT

Monitor output. MONOUT allows for monitoring of the analog input and is a high-impedance output. The gain

or mute is selected using control 1 register.

OUTM

Inverting output of the DAC. The OUTM output can be loaded with 600

Ω. OUTM is functionally identical with

and complementary to OUTP. OUTM can also be used alone for single-ended operation.

OUTP

Noninverting output of the DAC. The OUTP output can be loaded with 600

Ω. OUTP can also be used alone

for single-ended operation.

PWRDWN

Power down. When PWRDWN is pulled low, the device goes into a power-down mode, the serial interface

is disabled. However, all the register values are sustained and the device resumes full power operation without

reinitialization when PWRDWN is pulled high again. PWRDWN resets the counters only and preserves the

programmed register contents (see paragraph 2.2.2 for more information).

REFM

Voltage reference filter output. REFM is provided for low-pass filtering of the internal bandgap reference. The

optimal ceramic capacitor value is 0.1

µF and should be connected between REFM and REFP. DC voltage

at REFM is 0 V.

REFP

Voltage reference filter positive output. REFP is provided for low-pass filtering of the internal bandgap

reference. The optimal ceramic capacitor value is 0.1

µF and should be connected between REFP and REFM.

DC voltage at REFP is 3.2 V.

RESET

Reset. RESET initializes all of the internal registers to their default values. The serial port can be configured

to the default state accordingly. See section 6 and paragraph 2.2.1 for more information.

SCLK

I/O

Shift clock. The SCLK signal clocks serial data in through DIN and out through DOUT during the frame-sync

interval. When configured as an output (M/S high), SCLK is generated internally by multiplying the frame-sync

signal frequency by 256. When configured as an input (M/S low), SCLK is generated externally and must be

synchronous with the master clock and frame sync.

NOTES:

1. Separate analog and digital power and ground pins are supplied on this device. For best operation and results, the PC board designer

should utilize separate analog and digital power supplies as well as separate analog and digital ground planes.

2. All digital inputs and outputs are TTL compatible, unless otherwise noted (for DVDD = 5 V).

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