TLC320AD50CSLASHI datasheet(47/54 Pages) TI2

47 / 54 page

6–2

6.2

Control Register 2

Table 6–3. Control Register 2

DESCRIPTION

–

FLAG output value

–

Phone mode enable

–

Phone mode disable

–

Decimator FIR overflow flag (valid only during read cycle)

–

16-bit ADC mode

–

Not-16-bit ADC mode [(15+1)– bit mode]

–

Reserved (TLC320AD50C only)

–

FSD enable (TLC320AD52C only)

–

FSD disable (TLC320AD52C only)

–

Analog loopback enabled

–

Analog loopback disabled

Default value: 00000000

Writing 0s to the reserved bits is suggested.

6.3

Control Register 3

The following command contains the frame-sync delay (FSD) register address and loads D7 (MSB)–D0 into the FSD

FSD. The minimum data value for this portion of the register, bits D5–D0, is decimal 18.

Table 6–4. Control Register 3

DESCRIPTION

–

Number of SCLKs between FS and FSD

–

Binary number of slave devices (3 maximum for TLC320AC50C, 1 maximum for

TLC320AC52C)

Default value: 00000000

Writing 0s to the reserved bits is suggested.

6.4

Control Register 4

Table 6–5. Control Register 4

DESCRIPTION

–

Analog input gain = mute

–

Analog input gain = 12 dB

–

Analog input gain = 6 dB

–

Analog input gain = 0 dB

–

Analog output gain = mute

–

Analog output gain = – 12 dB

–

Analog output gain = – 6 dB

–

Analog output gain = 0 dB

–

Sample frequency select (N): fs = MCLK/(128 N) or MCLK/(512 N)

–

Bypass internal DPLL

–

Enable internal DPLL

Default value: 00000000

The value of the sample frequency divisor, N, is determined by the octal representation of bits D4–D6. Hence,

001 = 1, 010 = 2, etc. By setting D4–D6 to 000, N = 8 is selected.

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