TLC320AD50CSLASHI datasheet(38/54 Pages) TI2

38 / 54 page

4–5

4.3.8

DAC Channel Characteristics

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Dynamic range

Interchannel isolation

100

Gain error, 0 dB

VO = 0 dB at 1020 Hz

±0.3

Idle channel narrow band noise

0 – 4 kHz,

See Note 8

125

µV rms

VOO

Output offset voltage at OUT (differential)

DIN = All 0s

Analog output voltage, OUTP – OUTM

RL = 600 Ω typ (see Figure 2–17) with internal

reference and full-scale digital input,

See Note 9, differential

VPP

Total out of band energy (0.55 fs to 3 MHz)

–45

Channel delay

18/fs

NOTES:

8. The conversion rate is 8 kHz; the-out-of-band measurement is made from 4400 Hz to 3 MHz.

9. The digital input to the DAC channel at DIN is in 2s complement format. The TLC320AD50C/52C DAC is of the voltage-type and

requires a load resistor for current to voltage conversion.

4.3.9

Power Supply, AVDD = DVDD = 5 V, No Load

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

IDD (analog)

Power supply current ADC

Operating

IDD (analog)

Power supply current, ADC

Power down

IDD (PLL)

Power supply current PLL

Operating

IDD (PLL)

Power supply current, PLL

Power down

0.5

IDD (digital 1) Power supply current digital

Operating

IDD (digital 1) Power supply current, digital

Power down

µA

IDD (digital 2) Power supply current digital DVDD =3V

Operating

IDD (digital 2) Power supply current, digital, DVDD = 3 V

Power down

µA

Power dissipation

Operating

120

170

Power dissi ation

H/W-power down

7.5

4.3.10 Power-Supply Rejection, AVDD = DVDD = 5 V (see Note 10)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

AVDD

Supply voltage rejection ratio, analog supply

fi = 0 to fs/2

DVDD

Supply voltage rejection ratio, DAC channel

fi = 0 to 30 kHz

DVDD

Supply voltage rejection ratio, ADC channel

fi = 0 to 30 kHz

NOTE 10: Power supply rejection measurements are made with both the ADC and the DAC channels idle and a 200-mV peak-to-peak signal

applied to the appropriate supply.

4.4

Timing Characteristics (see Parameter Measurement Information)

4.4.1

Master Mode Timing Requirements

MIN

NOM

MAX

UNIT

td1

Delay time, SCLK

↑ to FS↓

tsu1

Setup time, DIN, before SCLK low

th1

Hold time, DIN, after SCLK low

td(CH–FDL) Delay time, SCLK high to FSD low (see Figure 5–1)

twH

Pulse duration, MCLK high

twL

Pulse duration, MCLK low

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