TLC320AD50CSLASHI datasheet(22/54 Pages) TI2

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2–7

2.2.2.2 Hardware Power Down

When PWRDWN is held low, the device enters the hardware power-down mode. In this state, the internal clock control

circuit and the differential outputs OUTP and OUTM are disabled. All other digital I/Os either are disabled or remain

in the state they were in immediately before power down. DIN cannot accept any data input. The device can only be

returned to normal operation by taking and holding PWRDWN high. When not holding the device in the hardware

power-down mode, PWRDWN should be tied high.

2.3

Master Clock Circuit

MCLK is the external master clock input. The internal clock circuit generates and distributes necessary clocks

throughout the device. An internal PLL circuit is used for upsampling to provide the appropriate clocks for the digital

filters and modulators.

When the device is in the master mode, SCLK and FS are derived from MCLK in order to provide clocking of the serial

communications between the device and its controller. When in the slave mode, SCLK and FS are both inputs.

2.4

Data Out (DOUT)

DOUT is placed in the high-impedance state on the rising edge of the frame sync. In the primary communication, the

data word is the ADC conversion result. In the secondary communication, the data is the register-read results when

requested by the read/write (R/W) bit. If a register read is not requested, the low eight bits of the secondary word are

all zeroes. The state of the master/slave (M/S) terminal is reflected by the MSB in secondary communication (DOUT,

bit DS15) and the LSB in the primary communication (DOUT, bit D0) while in 15 + 1 mode. When the device is in the

slave mode, DOUT remains in a high-impedance state until a nonzero value is written as a number of slaves in control

2.4.1

Data Out, Master Mode

In the master mode, DOUT is taken from the high-impedance state by the falling edge of the frame sync (FS) that

is assigned to DOUT. The most significant data bit then appears first on DOUT.

2.4.2

Data Out, Slave Mode

In the slave mode, DOUT is taken from the high-impedance state by the falling edge of the input frame sync (FS).

The most significant data bit then appears on DOUT. When in the slave mode, DOUT is not enabled until the control

3 register is programmed with the number of slaves. This must be done even if there is only one slave device.

2.5

Data In (DIN)

In a primary communication, the data word is the input digital signal to the DAC channel. If the (15+1)-bit data format

is used, the LSB (D0) is used to request a secondary communication. In a secondary communication, the data is the

control and configuration data that sets the device for a particular function (see Section 3, Secondary Serial

Communication for details).

2.6

FC (Hardware Secondary Communication Request)

The FC input provides for hardware requests for secondary communications. FC works in conjunction with the LSB

of the primary data word. The signal on FC is latched on the rising edge of the primary frame sync (FS). FC should

be tied low if not used.

2.7

Frame-Sync Function for TLC320AD50C

The frame-sync signal (FS) indicates the device is ready to send and receive data. The data transfer out of DOUT

and into DIN begins on the falling edge of the frame-sync signal.

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