TLC320AD50CSLASHI datasheet(16/54 Pages) TI2

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2–1

2 Detailed Description

2.1

Device Functions

2.1.1

Operating Frequencies and Filter Control

The sampling frequency is controlled by control register 4. When the internal PLL is enabled (D7=0), the sampling

frequency is derived from the following equation:

fs + Sampling (conversion) frequency +

MCLK

128

(1)

When the internal PLL is disabled (D7=1), the sampling frequency is derived from the following equation:

fs + Sampling (conversion) frequency +

MCLK

512

(2)

If the sampling frequency is lower than 7 kHz, the sampling frequency is derived from the master clock (MCLK) using

equation 2. The internal PLL must be bypassed. The PLL input clock for sampling frequencies lower than 7 kHz is

outside the working range for the PLL input clock.

The frequency of SCLK is derived from sampling frequency (fs) instead of MCLK. The equation is as follows:

SCLK

+ 256

(3)

The cutoff frequency of the filter can not be controlled by register programming. The filter response is shown in the

specification for an 8 kHz sample rate. This pass band scales linearly with the sample rate.

2.1.2

ADC Signal Channel

The input signal is amplified and applied to the ADC input. The ADC converts the signal into discrete output digital

words in 2s-complement data format, corresponding to the instantaneous analog-signal value at the sampling time.

These 16-bit (or 15-bit) digital words, representing sampled values of the analog input signal after the PGA, are

clocked out of the serial port (DOUT) at the positive edge of SCLK during the frame-sync interval, one bit for each

SCLK and one word for each primary communication interval (256 SCLKs). The 16-bit or (15 + 1)-bit ADC mode is

programmed into the device using control register 2. The default setting is the (15 + 1)-bit mode after power-up.

During secondary communication, the data previously programmed into the registers can be read out. This read

operation is accomplished by sending the appropriate register address (DS12 – DS8) with the read bit (DS13) set

to 1 in through DIN during present secondary communication. If a register read is not requested, all 16 bits are cleared

to 0 in the secondary communication. The timing sequence is shown in Figure 2–1 and Figure 2–2.

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