TLC320AD50CSLASHI datasheet(11/54 Pages) TI2

11 / 54 page

1–4

1.4

Ordering Information

PACKAGE

SMALL OUTLINE

PLASTIC DIP

(DW)

QUAD FLAT PACK

(PT)

°C to 70°C

TLC320AD50CDW

TLC320AD52CDW

TLC320AD50CPT

TLC320AD52CPT

–40

°C to 85°C

TLC320AD50IDW

1.5

Terminal Functions

TERMINAL

NAME

NO.

I/O

DESCRIPTION

ALTDATA

Alternate data. ALTDATA signals are routed to DOUT during secondary communication if the phone mode

is enabled using control 2 register.

AUXM

Inverting input to auxiliary analog input. AUXM requires an external single-pole antialias filter with a low output

impedance and should be tied to AVSS if not used.

AUXP

Noninverting input to auxiliary analog input. AUXP requires an external single-pole antialias filter with a low

output impedance and should be tied to AVSS if not used.

AVDD

Analog ADC power supply (5 V only) (see Note 1)

AVDD(PLL)

Analog power supply for the internal PLL (5 V only) (see Note 1)

AVSS

Analog ground (see Note 1)

AVSS(PLL)

Analog ground for the internal PLL (see Note 1)

DIN

Data input. DIN receives the DAC input data and register data from the external DSP (digital signal processor)

and is synchronized to SCLK and FS. Data is latched at the falling edge of SCLK when FS is low. DIN is at

high impedance when FS is not active.

DOUT

Data output. DOUT transmits the ADC output bits and register data, and is synchronized to SCLK. Data is

sent out at the rising edge of SCLK when FS is low. DOUT is at high impedance when FS is not activated.

When configured as a master, DOUT is active only during the appropriate time slot. DOUT is in high

impedance during the frame syncs for the slaves.

DVDD

Digital power supply (5 V or 3 V) (see Note 1)

DVSS

Digital ground (see Note 1)

Hardware secondary communication request. When FC is set to high, a secondary communication, followed

by the primary communication, will occur to transfer data between this device and the external controller. FC

is sampled and latched on the rising edge of FS at the end of the primary serial communication. See section

3 for details.

FILT

Bandgap filter. FILT is provided for decoupling of the bandgap reference, and provides 3.2 V. The optimal

capacitor value is 0.1

µF (ceramic). This voltage node should be loaded only with a high-impedance dc load.

FLAG

Output flag. During phone mode, FLAG contains the value set in control 2 register.

I/O

Frame sync. FS is an output when the device is configured as a master (M/S pin tied high). FS is an input when

the device is configured as a slave (M/S pin tied low). When configured as a slave, data will transfer when

FS goes low. FS is internally generated in the master mode for the master device and all slave devices. In

the master mode FS is low during data transfer.

FSD

Frame sync delayed output. The FSD (active-low) output synchronizes a slave device to the frame sync of

the master device. FSD is applied to the slave FS input and is the same duration as the master FS signal but

is delayed in time by the number of shift clocks programmed in the control 3 register.

INM

Inverting input to analog modulator. INM requires an external single-pole antialias filter with a low output

impedance.

INP

Noninverting input to analog modulator. INP requires an external single-pole antialias filter with a low output

impedance.

NOTES:

1. Separate analog and digital power and ground pins are supplied on this device. For best operation and results, the PC board designer

should utilize separate analog and digital power supplies as well as separate analog and digital ground planes.

2. All digital inputs and outputs are TTL compatible, unless otherwise noted (for DVDD = 5 V).

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