TLC320AD50CSLASHI datasheet(46/54 Pages) TI2

46 / 54 page

6–1

6 Register Set

Bits D12 through D8 in a secondary serial communication comprise the address of the register that is written with

data carried in D7 through D0. D13 determines a read or write cycle to the addressed register. When low, a write cycle

is selected.

The following table shows the register map.

Table 6–1. Register Map

D15

D14

D13

D12

D11

D10

No operation

Control 1

Control 2

Control 3

Control 4

6.1

Control Register 1

Table 6–2. Control Register 1

DESCRIPTION

–

Software reset

–

Software reset not asserted

–

Software power down (analog and filters)

–

Software power down (not asserted)

–

Select AUXP and AUXM for ADC

–

Select INP and INM for ADC

–

Select INP and INM for monitor

–

Select AUXP and AUXM for monitor

–

Monitor amplifier gain = – 18 dB (see Note 1)

–

Monitor amplifier gain = – 8 dB (see Note 1)

–

Monitor amplifier gain = 0 dB (see Note 1)

–

Monitor amp mute

–

Digital loopback asserted

–

Digital loopback not asserted

–

16-bit DAC mode (hardware secondary requests)

–

Not 16-bit DAC mode (software secondary requests) [(15+1)– bit mode]

Default value: 0 0 0 0 0 0 0 0

NOTE 1: These gains are for a single-ended input. The gain is 6 dB lower with a differential input.

A software reset is a one-shot operation and this bit is cleared to 0 after reset. It is not necessary to write a 0 to end

the master reset operation. Writing 0s to the reserved bits is suggested.

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