HCS08 datasheet(117/198 Pages) NXP

117 / 198 page

Analog-to-Digital Converter (S08ADC10V1)

MC9S08QD4 Series MCU Data Sheet, Rev. 6

Freescale Semiconductor

117

8.6.2

Sources of Error

Several sources of error exist for A/D conversions. These are discussed in the following sections.

8.6.2.1

Sampling Error

For proper conversions, the input must be sampled long enough to achieve the proper accuracy. Given the

maximum input resistance of approximately 7k

Ω and input capacitance of approximately 5.5 pF, sampling

to within 1/4LSB (at 10-bit resolution) can be achieved within the minimum sample window (3.5 cycles @

8 MHz maximum ADCK frequency) provided the resistance of the external analog source (RAS) is kept

below 5 k

Ω.

Higher source resistances or higher-accuracy sampling is possible by setting ADLSMP (to increase the

sample window to 23.5 cycles) or decreasing ADCK frequency to increase sample time.

8.6.2.2

Pin Leakage Error

Leakage on the I/O pins can cause conversion error if the external analog source resistance (RAS) is high.

If this error cannot be tolerated by the application, keep RAS lower than VDDAD /(2N*ILEAK) for less than

1/4LSB leakage error (N = 8 in 8-bit mode or 10 in 10-bit mode).

8.6.2.3

Noise-Induced Errors

System noise which occurs during the sample or conversion process can affect the accuracy of the

conversion. The ADC accuracy numbers are guaranteed as specified only if the following conditions are

met:

•

There is a 0.1

μF low-ESR capacitor from VREFH to VREFL.

•

There is a 0.1

μF low-ESR capacitor from VDDAD to VSSAD.

•

If inductive isolation is used from the primary supply, an additional 1

μF capacitor is placed from

VDDAD to VSSAD.

•VSSAD (and VREFL, if connected) is connected to VSS at a quiet point in the ground plane.

•

Operate the MCU in wait or stop3 mode before initiating (hardware triggered conversions) or

immediately after initiating (hardware or software triggered conversions) the ADC conversion.

— For software triggered conversions, immediately follow the write to the ADCSC1 with a WAIT

instruction or STOP instruction.

— For stop3 mode operation, select ADACK as the clock source. Operation in stop3 reduces VDD

noise but increases effective conversion time due to stop recovery.

•

There is no I/O switching, input or output, on the MCU during the conversion.

There are some situations where external system activity causes radiated or conducted noise emissions or

excessive VDD noise is coupled into the ADC. In these situations, or when the MCU cannot be placed in

wait or stop3 or I/O activity cannot be halted, these recommended actions may reduce the effect of noise

on the accuracy:

•

Place a 0.01

μF capacitor (CAS) on the selected input channel to VREFL or VSSAD (this will

improve noise issues but will affect sample rate based on the external analog source resistance).

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