HCS08 datasheet(184/198 Pages) NXP

184 / 198 page

Appendix A Electrical Characteristics

MC9S08QD4 Series MCU Data Sheet, Rev. 6

184

Freescale Semiconductor

A.7

Internal Clock Source Characteristics

Table A-7. Internal Clock Source Specifications

Characteristic

Symbol

Min

Typ1

1 Data in Typical column was characterized at 3.0 V and 3.0 V, 25

°C or is typical recommended value.

Max

Unit

Average internal reference frequency - untrimmed

fint_ut

31.25

41.66

kHz

Average internal reference frequency - trimmed

fint_t

—

31.25

—

kHz

DCO output frequency range - untrimmed

fdco_ut

12.8

21.33

MHz

DCO output frequency range - trimmed

fdco_t

—16

—

MHz

Resolution of trimmed DCO output frequency at fixed voltage and

temperature (Consumer and Industrial MC9S08QDx)2

2 Characterized, but not tested.

Δf

dco_res_t

——

± 0.2

%fdco

Resolution of trimmed DCO output frequency at fixed voltage and

temperature (Automotive S9S08QDx)2

–40

°C to 0°C

0 to 125

°C

——

± 0.3

± 0.2

Total deviation of trimmed DCO output frequency over voltage and

temperature 2

Consumer and Industrial MC9S08QDx

Automotive S9S08QDx

Δf

dco_t

——

± 2

± 3

%fdco

FLL acquisition time 2,3

3 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing

from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference,

this specification assumes it is already running.

tacquire

1ms

Long term Jitter of DCO output clock (averaged over 2 ms interval) 4

4 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f

BUS.

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise

injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for

a given interval.

CJitter

——

0.6

%fdco

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