HCS08 datasheet(175/198 Pages) NXP

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Appendix A Electrical Characteristics

MC9S08QD4 Series MCU Data Sheet, Rev. 6

Freescale Semiconductor

175

A.4

ESD Protection and Latch-Up Immunity

Although damage from electrostatic discharge (ESD) is much less common on these devices than on early

CMOS circuits, normal handling precautions must be used to avoid exposure to static discharge.

Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels

of static without suffering any permanent damage.

All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade

Integrated Circuits. During the device qualification ESD stresses were performed for the human body

model (HBM), the machine model (MM) and the charge device model (CDM).

A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device

specification. Complete DC parametric and functional testing is performed per the applicable device

specification at room temperature followed by hot temperature, unless specified otherwise in the device

specification.

A.5

DC Characteristics

This section includes information about power supply requirements and I/O pin characteristics.

Table A-3. ESD and Latch-up Test Conditions

Model

Description

Symbol

Value

Unit

Human

Body

Series resistance

1500

Storage capacitance

100

Number of pulses per pin

—

Machine

Series resistance

Storage capacitance

200

Number of pulses per pin

—

Latch-up

Minimum input voltage limit

– 2.5

Maximum input voltage limit

7.5

Table A-4. ESD and Latch-Up Protection Characteristics

No.

Rating1

1 Parameter is achieved by design characterization on a small sample size from typical devices

under typical conditions unless otherwise noted.

Symbol

Min

Max

Unit

Human body model (HBM)

VHBM

± 2000

—

Machine model (MM)

VMM

± 200

—

Charge device model (CDM)

VCDM

± 500

—

Latch-up current at TA = 85°CILAT

± 100

—

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