HCS08 datasheet(170/198 Pages) NXP

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MC9S08QD4 Series MCU Data Sheet, Rev. 6

170

Freescale Semiconductor

12.3.1.2

BDC Breakpoint Match Register (BDCBKPT)

This 16-bit register holds the address for the hardware breakpoint in the BDC. The BKPTEN and FTS

control bits in BDCSCR are used to enable and configure the breakpoint logic. Dedicated serial BDC

commands (READ_BKPT and WRITE_BKPT) are used to read and write the BDCBKPT register but is

not accessible to user programs because it is not located in the normal memory map of the MCU.

Breakpoints are normally set while the target MCU is in active background mode before running the user

application program. For additional information about setup and use of the hardware breakpoint logic in

the BDC, refer to Section 12.2.4, “BDC Hardware Breakpoint.”

12.3.2

System Background Debug Force Reset Register (SBDFR)

This register contains a single write-only control bit. A serial background mode command such as

WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are

ignored. Reads always return 0x00.

Wait or Stop Status — When the target CPU is in wait or stop mode, most BDC commands cannot function.

However, the BACKGROUND command can be used to force the target CPU out of wait or stop and into active

background mode where all BDC commands work. Whenever the host forces the target MCU into active

background mode, the host must issue a READ_STATUS command to check that BDMACT = 1 before

attempting other BDC commands.

0 Target CPU is running user application code or in active background mode (was not in wait or stop mode when

background became active)

1 Target CPU is in wait or stop mode, or a BACKGROUND command was used to change from wait or stop to

active background mode

WSF

Wait or Stop Failure Status — This status bit is set if a memory access command failed due to the target CPU

executing a wait or stop instruction at or about the same time. The usual recovery strategy is to issue a

BACKGROUND command to get out of wait or stop mode into active background mode, repeat the command

that failed, then return to the user program. (Typically, the host would restore CPU registers and stack values and

re-execute the wait or stop instruction.)

0 Memory access did not conflict with a wait or stop instruction

1 Memory access command failed because the CPU entered wait or stop mode

DVF

Data Valid Failure Status — This status bit is not used in the MC9S08QD4 series because it does not have any

slow access memory.

0 Memory access did not conflict with a slow memory access

1 Memory access command failed because CPU was not finished with a slow memory access

Table 12-2. BDCSCR Register Field Descriptions (continued)

Field

Description

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