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HCS08 bảng dữ liệu(PDF) 163 Page - NXP Semiconductors

tên linh kiện HCS08
Giải thích chi tiết về linh kiện  HCS08 Microcontrollers
PDF  198 Pages
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HCS08 bảng dữ liệu(HTML) 163 Page - NXP Semiconductors

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Development Support
MC9S08QD4 Series MCU Data Sheet, Rev. 6
Freescale Semiconductor
163
Figure 12-3. BDC Target-to-Host Serial Bit Timing (Logic 1)
Figure 12-4 shows the host receiving a logic 0 from the target HCS08 MCU. Because the host is
asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on
BKGD to the start of the bit time as perceived by the target MCU. The host initiates the bit time but the
target HCS08 finishes it. Because the target wants the host to receive a logic 0, it drives the BKGD pin low
for 13 BDC clock cycles, then briefly drives it high to speed up the rising edge. The host samples the bit
level about 10 cycles after starting the bit time.
HOST SAMPLES BKGD PIN
10 CYCLES
BDC CLOCK
(TARGET MCU)
HOST DRIVE
TO BKGD PIN
TARGET MCU
SPEEDUP PULSE
PERCEIVED START
OF BIT TIME
HIGH-IMPEDANCE
HIGH-IMPEDANCE
HIGH-IMPEDANCE
BKGD PIN
R-C RISE
10 CYCLES
EARLIEST START
OF NEXT BIT



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