ADIN3310BBCZ datasheet(25/86 Pages) AD

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25 / 86 page

Data Sheet

ADIN3310/ADIN6310

PIN CONFIGURATION AND PIN DESCRIPTIONS

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Rev. A | 25 of 86

ADIN6310

Figure 13. ADIN6310 Pin Configuration (Top View, Looking Through the Device)

Table 14. Pin Function Descriptions

ADIN6310 Ball No.

Mnemonic

Type1

Internal

Termination at

Reset2

Power

Domain2

Description

Clock Interface

XTAL_IN/CLK_IN

High-Z

VDD3P3

Input for Crystal (XTAL_IN).

Single-Ended 25 MHz Reference Clock (CLK_IN).

XTAL_OUT

High-Z

VDD3P3

Second Terminal for Crystal Connection. If using a single-ended reference

clock on XTAL_IN/CLK_IN, leave XTAL_OUT open circuit.

CLK_OUT

High-Z

VDD3P3

Analog Reference Clock Output. The 25 MHz, 3.3 V reference clock from

the crystal oscillator.

Digital

H14

RESET_N

Pull-down

VDDIO_A

Active Low, Reset Input. RESET_N requires an external pull-down. Hold low

for >10 μs.

J15

TIMER0/INT

I/O

Pull-up

VDDIO_A

Timer or General-Purpose Input and Output (GPIO). When using the SPI

port, TIMER0 acts as an interrupt output to the host. The boot strapping pin

is used to define the host interface origin and operation.

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