ADIN3310BBCZ datasheet(33/86 Pages) AD

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Data Sheet

ADIN3310/ADIN6310

THEORY OF OPERATION

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Rev. A | 33 of 86

SWITCH OVERVIEW

The ADIN3310 and ADIN6310 are 3-port and 6-port Gigabit Ether-

net TSN switches with integrated security primarily designed for

industrial Ethernet applications. Each port can be configured to op-

erate at different speeds. These switches are designed to pair with

Analog Devices PHY layer devices, such as ADIN1100, ADIN1200,

and ADIN1300, to form a low power, low latency system over

RMII and RGMII. Optionally four of the ADIN6310 ports and two of

the ADIN3310 ports support SGMII and serdes interfaces allowing

backplane connections and connectivity to SFP modules.

Throughout this data sheet, references to the switch apply to both

the ADIN3310 and the ADIN6310. The only difference between the

two devices is the number of ports.

The switch supports the suite of IEEE 802.1 time sensitive net-

working bridging features required by the IEEE 60802 standard

providing QoS for latency sensitive streams.

The device also includes hardware capabilities to support PRP or

HSR redundancy protocols, thereby offloading the host processor.

For legacy support, two of the ports (Port 1 and Port 2) integrate

Analog Devices proprietary real-time Ethernet multiprotocol switch

(REMS) technology that allows simple interfacing to classical 100

Mbps industrial Ethernet protocols, such as the following:

►

PROFINET RT (Class B) and PROFINET IRT (Class C)

►

EtherNet/IP with device level ring (DLR)

►

POWERLINK

►

Modbus TCP

Software drivers are provided for the host to work in conjunction

with the switch to implement the industrial Ethernet protocol stacks.

Two host interface options are supported: Ethernet or SPI standard,

dual, or quad SPI). If an Ethernet host interface is selected, this

port can operate as a control plane and a data plane to the host,

leaving five or two Ethernet ports available for industrial Ethernet

applications, for the ADIN6310 or ADIN3310, respectively. The host

interface may be on a different voltage domain than the connections

to the external PHY layer devices, VDDIO_A vs. VDDIO_B, allow-

ing flexibility in choosing these voltages to allow simple interfacing

while conserving power.

PORT OVERVIEW

Figure 24 shows a simplified overview of a port transmit and

receive. The port front end supports RGMII and RMII on all six ports

and SGMII on four ports (Port 1 to Port 4) of the ADIN6310, and the

ports are independent; therefore, they can operate different speeds

or interfaces. Interface details are discussed further in the Ethernet

Interfaces section.

During initial configuration, the host configures the switch ports for

the desired connectivity using the SES_InitializePorts() application

programing interface (API) (see the SES_switch.h file for further

details, which is available as part of the software drivers from the

ADIN6310 product page). As part of this configuration, the user has

the ability to enable all ports or keep unused ports disabled. The

host identifies how each port must be configured, what MAC inter-

face, port speed, and whether there is an Ethernet PHY connected

to the port. The initialization can also perform any PHY-related

configuration needed.

The receive MAC processes the incoming frame by checking

whether the frame size is within the minimum and maximum rang-

es, verifying the interframe gap (IFG), the preamble and the start

frame delimiter (SFD), determining if the frame is preemptable or

has been preempted, and assessing the start mPacket delimiter

(SMD) value, order, and fragment count. The destination address,

source address, and VLAN tag are extracted for use in filtering

and address lookup, and the MAC calculates the cyclic redundancy

check (CRC) of the frame and compares it to the frame check

sequence (FSC). Any frames found to be in error are discarded.

Frames that pass the various checks continue to be processed

through the receive path.

While the various checks are happening, the frame is being for-

warded onto the receive path to be passed to the transmit paths of

the other ports. The transmit ports buffer the frame until all appropri-

ate information is gathered and routing decisions are complete.

Figure 24. Simplified Port Transmit and Receive

The transmit block for each port supports eight priority queues and

implements strict priority scheduling by default.

MAC, eMAC, and pMAC

The MAC consists of an express MAC (eMAC) and a preemptable

MAC (pMAC) to support frame preemption (Qbu). The eMAC unit

handles packets from the express queues and is capable of send-

ing cut-through or store and forward packets. The pMAC handles

packets from the preemptable queues and also monitors express

queues to determine whether to fragment an active preemptable

packet. The MAC verifies proper assembly of preemptable traffic

by verifying proper order and combination of SMDs, continuation

SMDs (SMD-Cs), and fragmentation counts, it also identifies any

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