ADIN3310BBCZ datasheet(29/86 Pages) AD

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Data Sheet

ADIN3310/ADIN6310

PIN CONFIGURATION AND PIN DESCRIPTIONS

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Rev. A | 29 of 86

Table 14. Pin Function Descriptions (Continued)

ADIN6310 Ball No.

Mnemonic

Type1

Internal

Termination at

Reset2

Power

Domain2

Description

C12

P5_RXD0

Pull-up

VDDIO_B

See Port 0.

A13

P5_RXD1

Pull-down

VDDIO_B

See Port 0.

B12

P5_RXD2

Pull-down

VDDIO_B

See Port 0.

A12

P5_RXD3

Pull-up

VDDIO_B

See Port 0.

B13

P5_RXCTL

Pull-down

VDDIO_B

See Port 0.

C11

P5_LINK

Pull-down

VDDIO_B

See Port 0.

Other

Joint Test Action Group (JTAG) Access.

D16

TDO

N/A

VDDIO_A

JTAG Test Data Output.

E16

TDI

N/A

VDDIO_A

JTAG Test Data Input,

F15

TCK

N/A

VDDIO_A

JTAG Test Clock.

F16

TMS

N/A

VDDIO_A

JTAG Test Mode Select.

G16

TEST_EN

N/A

VDDIO_A

Test Enable. JTAG mode enabled when TEST_EN is pulled high. For

normal operation, pull TEST_EN low or connect directly to ground if JTAG

not used.

Power3

D4, D6, D7, D11, E4,

F5, G6, G12, H6,

H12, J12, K4, K6,

K12, L5, L12, M5,

M7 to M9, M11, M12,

VDDCORE

N/A

Supply to the Digital and Analog Core, 1.1 V ± 5%. Place decoupling

capacitors with respect to DGND.

VDDCORE_PLL

N/A

Supply for the Analog Core, 1.1 V ± 5%. Place decoupling capacitors with

respect to VSSCORE_PLL.

D10, N10

VDDCORE_DLL

N/A

Supply for the Analog Core, 1.1 V ± 5%. Place decoupling capacitors with

respect to VSSCORE_DLL.

E12, F12, F13, K13,

L13, M13

VDDIO_A

N/A

Supply for the Host Port (RGMII and RMII Port 0, SPI, JTAG).

D8, D9, D12, D13,

E13, G13, H13, J13,

N7, N8, N9, N11,

N12

VDDIO_B

N/A

Supply for the RGMII and RMII Port 1 to Port 5, MDIO Interface.

H5, J5, K5, F14

VDD3P3

N/A

Analog Supply for the Analog, Crystal, and Clocking Circuitry. Place

decoupling capacitors with respect to VSS3P3.

E5, F4, L4, M4

VDD_SGMII

N/A

Supply for the SGMII on Port 1 to Port 4. Where an application does not use

the SGMII, connect the VDD_SGMII pins directly to VSS_SGMII ground on

the board.

Ground

F2, H3, J3, K3

VSS3P3

N/A

Ground for the Analog, Crystal, and Clock Circuit.

M10, E10

VSSCORE_DLL

N/A

Ground for the Analog Core.

VSSCORE_PLL

N/A

Ground for the Analog Core.

F1, C1, D3, E3, F3,

M1, M2, N3, P3, R1

VSS_SGMII

N/A

Ground for the SGMII on Port 1 to Port 4.

A1, A16, C4, C10,

C14, D5, E6, E7 to

E9, E11, F6 to F11,

G7 to G11, G14,

G15, H7 to H11, J6

to J11, K7 to K11,

L6to L11, M6, N5,

N6, N13, P11to P13,

T1, T16

DGND

N/A

Digital Ground.

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