ADIN3310BBCZ datasheet(44/86 Pages) AD

44 / 86 page

Data Sheet

ADIN3310/ADIN6310

INTERFACES

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Rev. A | 44 of 86

SERIAL INTERFACE, SPI

The switch contains a synchronous SPI-compatible serial interface

that can be used as the host interface. SPI supports 32-bit data

transfers, is a target interface, and can be a standard SPI or a dual

or quad SPI. Table 18 lists the relevant pins for the different SPI

interface modes. Configuration of the host interface mode can be

made using external boot strapping (see the Table 22 section). In

SPI mode, the interface allows full duplex operation and half duplex

communication in dual or quad SPI.

The transactions on the interface are consumed by the packet

assist engine and facilitate communications between the switch

and the host processor. The SPI port provides a communication

medium for low to medium performance systems with higher per-

formance processors or field-programmable gate arrays (FPGAs)

interfacing directly to the RMII, RGMII or SGMII on one of the

Ethernet ports.

Chip Select, SPI_SS

The active low, chip select pin (SPI_SS) enables and disables

the SPI port. When SPI_SS is high, the device is not selected,

and the serial data outputs (SPI_SIOx) are high impedance. When

SPI_SS is brought low, the device is selected, and commands can

be written to or read from the device.

Serial Clock, SPI_SCLK

The serial clock input is used to synchronize data to and from the

packet assist engine of the switch. The maximum SCLK frequency

is 38 MHz.

Serial Data Input and Output, SPI_SIOx

The switch supports standard SPI, dual SPI, and quad SPI commu-

nications. The device has four SPI_SIOx pins. When operating with

a standard SPI, the SPI_SIO0/SDI is the unidirectional serial data

input line for write operations and clocked in on the rising edge of

SPI_SCLK. The SPI_SIO1/SDO is the unidirectional data output for

reads and is clocked out on the falling edge of SPI_SCLK.

For dual and quad SPI, commands use the bidirectional SPI_SIOx

pins to read and write data.

Data lines are only driven in response to a read command.

Table 18. SPI Pin Operation

Mnemonic

Quad SPI

Dual SPI1

SPI1

SPI_SS

SPI_SCLK

SCLK

SPI_SIO0

SIO0

SDI

SPI_SIO1

SIO1

SDO

SPI_SIO2

SIO2

N/A

SPI_SIO3

SIO3

N/A

1 N/A means not applicable.

Interrupt, INT

The TIMER0/INT pin provides a single interrupt output from the

switch to the host and is used to coordinate SPI operations. The

INT function is a shared function on the TIMER0/INT pin and is

managed via the packet assist engine software, which is available

on the ADIN6310 product page.

Dual and Quad SPI Interactions

Figure 30 shows an overview of the bit and byte ordering for

quad SPI read communications. Reads require a two clock period

turnaround before the data is available on the SPI_SIOx pins. The

SPI_SIOx pins are driven low during this two clock turnaround time.

The write transaction looks similar in terms of format; however,

without the turnaround, the first nibble of data immediately follows

the second nibble of instruction byte. Data is transmitted and

received MSB first.

Dual SPI transactions are similar, SPI_SIO1 carries the most sig-

nificant bit of a pair, and the most significant pair of a byte is

transmitted first. Similarly, reads use a two clock period turnaround.

Finally, quad SPI transactions transmit the most significant nibble

first, with the most significant bit of the nibble on SPI_SIO3 as

shown in Figure 30. Quad SPI also requires a two clock period

turnaround.

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