ADIN3310BBCZ datasheet(19/86 Pages) AD

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Data Sheet

ADIN3310/ADIN6310

ABSOLUTE MAXIMUM RATINGS

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Rev. A | 19 of 86

Table 9. Absolute Maximum Ratings

Parameter

Rating

VDD3P3 to VSS3P3

−0.3 V to +3.63 V

VDDCORE to DGND

−0.3 V to +1.26 V

VDDCORE_PLL to VSSCORE_DLL

−0.3 V to +1.26 V

VDDCORE_DLL to VSSCORE_DLL

−0.3 V to +1.26 V

VDD_SGMII to VSS_SGMII

−0.3 V to +3.63 V

VDDIO_A to DGND

−0.3 V to +3.63 V

VDDIO_B to DGND

−0.3 V to +3.63 V

VSS3P3 to DGND

−0.3 V to +0.3 V

VSSCORE_x to DGND

−0.3 V to +0.3 V

VSS_SGMII to VSS3P3

−0.3 V to +0.3 V

Port 0 RMII/RGMII MAC Interface to GND

(P0_TXxx and P0_RXxx)1

−0.3 V to VDDIO_A + 0.3 V

Port 1 to Port 5 RMII/RGMII MAC Interface to

GND (Px_TXxx and Px_RXxx)2

−0.3 V to VDDIO_B + 0.3 V

SGMII MAC Interface to GND (Px_STXN,

Px_STXPxx)

−0.3 V to VDDCORE + 0.3 V

SGMII MAC Interface to GND (Px_SRXN,

Px_SRXPxx)

−0.3 V to VDDCORE + 0.5 V

XTAL_IN, CLK_IN, XTAL_OUT, and CLK_OUT

−0.3 V to VDD3P3 + 0.3 V

RESET_N, TIMERx, GPIOx, TDO, TDI, TCK,

TMS, and TEST_EN

−0.3 V to VDDIO_A + 0.3 V

SPI (SPI_xx) to DGND

−0.3 V to VDDIO_A + 0.3 V

Management Interface (MDC and MDIO)

−0.3 V to +3.63 V

Temperature

Industrial

−40°C to +105°C

Storage Range

−65°C to +150°C

TJ Maximum

125°C

Lead

JEDEC industry-standard

Power Dissipation

(TJ maximum − TA)/θJA

Soldering

J-STD-020

1 All Port 0 pins, including P0_LINK and P0_RSTN.

2 All Port 1 to Port 5 pins including Px_LINK and Px_RSTN.

Stresses at or above those listed under Absolute Maximum Ratings

may cause permanent damage to the product. This is a stress

rating only; functional operation of the product at these or any other

conditions above those indicated in the operational section of this

specification is not implied. Operation beyond the maximum operat-

ing conditions for extended periods may affect product reliability.

THERMAL RESISTANCE

Thermal performance is directly linked to PCB design and operating

environment. Close attention to PCB thermal design is required.

θJA is the natural convection junction to ambient thermal resistance

measured in a one cubic foot sealed enclosure.

θJC is the junction to case thermal resistance.

Table 10. Thermal Resistance

Package Type

θJA

θJC

Unit

256-Ball CSP_BGA

20.841

5.961

°C/W

202

Not applicable

°C/W

196-Ball CSP_BGA

211

°C/W

202

Not applicable

°C/W

1 Based on simulated data using a JEDEC 2s2p thermal test board (with

enhanced cu density) in a JEDEC natural convection environment. See JEDEC

specification JESD-51 for details.

2 Test Condition 1: thermal impedance measured on Analog Devices, Inc.,

hardware, 4S4P test board.

ELECTROMAGNETIC COMPATIBILITY (EMC)

PERFORMANCE

EMC testing was performed using the EVAL-ADIN6310EBZ evalua-

tion hardware against the following EMC test standards:

►

IEC 61000-4-5 surge (Class A ±4 kV)

►

IEC 61000-4-4 electrical fast transient (EFT) (Class A ±1 kV,

Class B ±4 kV)

►

IEC 61000-4-2 ESD (Class A ±4 kV, Class B ±8 kV contact

discharge)

►

IEC 61000-4-3 radiated immunity

►

80 MHz to 1 GHz (Class A: 10 V/m)

►

1 GHz to 3.2 GHz (Class A: 3 V/m)

►

3.2 GHz to 6 GHz (Class A: 1 V/m)

►

IEC 61000-4-6 conducted immunity (Class A: 10 V)

►

EN 55032 radiated emissions (Class A)

►

EN 55032 conducted emissions (Class B)

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