ADIN3310BBCZ datasheet(12/86 Pages) AD

12 / 86 page

Data Sheet

ADIN3310/ADIN6310

SPECIFICATIONS

analog.com

Rev. A | 12 of 86

Table 1. Electrical Characteristics1 (Continued)

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Crystal Oscillator RMS Jitter

1.8

Clock Input Frequency (CLK_IN)

MHz

Requirements for external clock applied to XTAL_IN pin;

VDD3P3 voltage domain

Duty Cycle

Input Voltage Range

3.135

3.3

3.465

FLASH MEMORY

Endurance

10,000

Cycles

Data Retention

Years

TJ = 125°C

Years

TJ = 85°C

1 Specifications may be subject to change.

2 When all six ports operate at 1 Gbps, use a VDDIO_B supply voltage of 1.8 V or 2.5 V to minimize power consumption.

3 Enabling SendList on the ADIN3310 adds 15 mA to the VDDCORE current consumption.

4 Guaranteed by design.

5 minByteCnt represents the number of received bytes before a cut-through frame is queued for transmission. The purpose is to remove the latency jitter due to access time

in the lookup table. The default setting for minByteCnt = 0x20. For this specification, minByteCnt was reduced to 0x10 so that when the VLAN is received and the lookup

table provides the routing information, the frame is immediately queued for transmission. Using lower numbers can decrease latency and increase jitter.

6 Latency from the SGMII to SGMII port = SGMII Receive + Bridge Latency + SGMII Transmit. Latency from the SGMII to RGMII port = SGMII Receive + Bridge Latency.

Latency from the RGMII to SGMII port = Bridge Latency + SGMII Transmit.

7 Where load capacitance (CL) = ((C1 × C2)/(C1 + C2) + CSTRAY), where CSTRAY is the stray capacitance including routing and package parasitics.

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