ADIN3310BBCZ datasheet(46/86 Pages) AD

46 / 86 page

Data Sheet

ADIN3310/ADIN6310

INTERFACES

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Rev. A | 46 of 86

Communication over SPI

In applications using any of the SPI options as the host interface

to the switch, the switch uses the TIMER0 hardware pin as an

interrupt to indicate availability of data to the host. If the host

uses Ethernet as the preferred interface, then the TIMER0 pin

does not act as interrupt pin and is available as a timer pin.

For all SPI modes, the host must connect the TIMER0 pin to an

available GPIO pin on the host. A rising edge event on this pin

must trigger a software interrupt on the host side to prompt a read

of the message from the switch. In this interrupt service routine,

the hardware abstract layer (HAL) interface read function must be

called to read data from the scaleable Ethernet switch (SES) and

then call the SES_ReceiveMessage() API of the driver, which is

available as part of the software drivers from the ADIN6310 product

page. The response from the SES for this interface read call results

in the length of bytes available to read from the switch. The host

must call another HAL interface read with this length of bytes to

the switch. Finally, the response data of this call must be passed

to the SES_ReceiveMessage() API. Ideally, the host dedicates a

separate thread for this event or has a interrupt service routine

(ISR).

PHY MDC AND MDIO INTERFACE

The switch has a controller MDC and MDIO interface, which is a

2-wire bus used to manage control and status of the PHY layers

connected to the switch. The PHY layers act as targets on this bus,

each with its own distinct address. The PHY addresses are set with

external strapping resistors that are sampled at reset. Alternatively,

the switch can set unique PHY address directly with dedicated

internal pull-up/pull-down resistors per port. This interface can have

up to 32 target devices connected. The MDIO interface consists of

a clock pin (MDC) and a bidirectional data line (MDIO). The clock

is an output from the switch and an input to the PHY layers. The

MDIO pin requires an external 1.5 kΩ resistor pulled to VDDIO_B.

The data line is typically driven from the switch, except when a read

is commanded to one of the PHY layers.

The bus is controlled by the packet assist engine in the switch. If

an external host processor requires access to the PHY registers, it

must request this access through its general interface and let the

packet assist engine perform the bus transaction. The frame format

is standard for this type of interface, and each instruction consists

of the following:

►

Preamble: establishes synchronization at beginning of the frame.

►

Start of frame: 01 indicates the start of the frame.

►

OP: the operation code indicates the type of frame transaction;

10 for read, and 01 for write.

►

PHYAD: PHY address. MSB first, only the PHY layer with the

matching PHY address responds.

►

REG ADDR: register address, MSB first.

►

TA: used to avoid contention during a read transition, with 2-bit

time spacing between the register address field and data field.

►

DATA: 16-bit field, MSB first.

►

IDLE: high-Z state, the MDIO line is pulled high by the pull-up

resistor.

Table 19. Frame Format

Operation

Preamble

Start of Frame

PHYAD[4:0]

REG ADDR[4:0]

DATA[15:0]

IDLE

Read

32 1s

AAAAA

RRRRR

d … d

Write

32 1s

AAAAA

RRRRR

d … d

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