ADIN3310BBCZ datasheet(21/86 Pages) AD

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Data Sheet

ADIN3310/ADIN6310

PIN CONFIGURATION AND PIN DESCRIPTIONS

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Rev. A | 21 of 86

ADIN3310

Figure 12. ADIN3310 Pin Configuration (Top View, Looking Through the Device)

Table 13. Pin Function Descriptions

ADIN3310 Ball No. Mnemonic

Type1

Internal

Termination at

Reset2

Power

Domain

Description

Clock Interface

XTAL_IN/CLK_IN

High-Z

VDD3P3

Input for Crystal (XTAL_IN).

Single-Ended 25 MHz Reference Clock (CLK_IN).

XTAL_OUT

High-Z

VDD3P3

Second Terminal for Crystal Connection. If using a single-ended reference

clock on XTAL_IN/CLK_IN, leave XTAL_OUT open circuit.

CLK_OUT

High-Z

VDD3P3

Analog Reference Clock Output. The 25 MHz, 3.3 V reference clock from the

crystal oscillator.

Digital

A13

RESET_N

Power-down

VDDIO_A

Active Low and Reset Input. RESET_N requires an external pull-down. Hold

low for >10 μs.

F14

TIMER0/INT

I/O

Power-up

VDDIO_A

Timer or General Purpose Input and Output (GPIO). When using the SPI port,

TIMER0 acts as interrupt output to the host. The boot strapping pin is used to

define the host interface origin and operation.

F13

TIMER1

I/O

Power-up

VDDIO_A

TImer or GPIO. The boot strapping pin is used to define the host interface

origin and operation.

E14

TIMER2

I/O

Power-down

VDDIO_A

Timer or GPIO. The boot strapping pin is used to define the host interface

origin and operation.

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