ADIN3310BBCZ datasheet(55/86 Pages) AD

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Data Sheet

ADIN3310/ADIN6310

POWER ARCHITECTURE

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Rev. A | 55 of 86

POWER CONSUMPTION AND THERMAL

CONSIDERATIONS

Worst case power consumption conditions are all six ports operat-

ing at 1 Gbps. Careful consideration is required when choosing the

VDDIO_B power supply rail to keep the die temperature within the

operating temperature range. When operating at 1 Gbps on all six

ports, use VDDIO_B at 1.8 V or 2.5 V. Operating at VDDIO_B =

3.3 V when all ports are at a 1 Gbps speed is not supported. Table

28 includes per port typical power parameters for all VDDIO supply

voltages because various use cases may have the ports operating

a mix of PHY technology and speeds.

Table 28. Power Consumption Per Port

Use Case

VDDIO

Unit

1.8 V

2.5 V

3.3 V

Base Power1

126.5

1 Gbps RGMII

36.6

60.7

95.7

100 Mbps RGMII

17.05

10 Mbps RGMII

6.2

7.4

9.35

1 Gbps SGMII

59.2

68.4

81.4

1000BASE-KX

65.8

100BASE-FX

55.9

59.95

1 Base power is the background power consumption for the chip. Total Power

Consumption = Base Power + Each Port Power.

POWER SUPPLY DECOUPLING

It is recommended to decouple each of the supply rails with the

capacitors detailed in Table 29 to their relevant grounds. Place the

smaller decoupling capacitor (0.1 μF) as close to the relevant balls

as possible and ensure that the capacitor ground is routed directly

into the plane.

Table 29. Recommended Decoupling

Supply Name

Capacitor Value

VDD3P3 to VSS3P3

One 4.7 μF per group, 0.1 μF per ball

VDD_SGMII to VSS_SGMII

One 4.7 μF per group, 0.1 μF per ball

VDDIO_A to DGND

One 4.7 μF per group, 0.1 μF per ball

VDDIO_B to DGND

One 4.7 μF per group, 0.1 μF per ball

VDDCORE to DGND

One 20 μF and 0.47 μF per group, 0.1 μF

per ball

VDDCORE_PLL to VSSCORE_PLL

0.1 μF and 0.01 μF

VDDCORE_DLL to VSSCORE_DLL

0.1 μF per ball

When placing the decoupling capacitors, prioritize the locations

detailed in Table 30 and detailed in Table 31 with capacitors con-

nected across these nets.

Table 30. ADIN3310 Layout Prioritization for Bypass Capacitors

Supply

Ground

Ball Number

VDDCORE_DLL

VSSCORE_DLL

L9 to L8

VDDCORE_PLL

VSSCORE_PLL

D4 to D3

VDD3P3

VSS3P3

G4 to G3

VSS3P3

F3 to E3

VSS3P3

E2 to D2

Table 31. ADIN6310 Layout Prioritization for Bypass Capacitors

Supply

Ground

Ball Number

VDDCORE_DLL

VSSCORE_DLL

N10 to M10

VSSCORE_DLL

D10 to E10

VDDCORE_PLL

VSSCORE_PLL

G5 to G3

VDD3P3

VSS3P3

H5 to H3

VSS3P3

J5 to J3

VSS3P3

K5 to K3

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