AM79C940KCSLASHW datasheet(67/144 Pages) AMD

67 / 144 page

Am79C940

modified

backoff

algorithm.

EMBA is cleared by activation of

the RESET pin or SWRST bit.

Bit 4

RES

Reserved.

Read

zeroes.

Always write as zeroes.

Bit 3

DRCVPA

Disable

Receive

Physical

Address. When set, the physical

address detection (Station or

node ID) of the MACE device will

be disabled. Packets addressed

to the nodes individual physical

address will not be recognized

(although the packet may be

accepted by the EADI mecha-

nism). DRCVPA is cleared by

activation of the RESET pin or

SWRST bit.

Bit 2

DRCVBC

Disable

Receive

Broadcast.

When set, disables the MACE

device

from

responding

broadcast messages. Used for

protocols that do not support

broadcast addressing, except as

a function of multicast. DRCVBC

is cleared by activation of the

RESET

SWRST

bit

(broadcast messages will be

received).

Bit 1

ENXMT

Enable

Transmit.

Setting

ENXMT = 1 enables transmis-

sion. With ENXMT = 0, no trans-

mission will occur. If ENXMT is

written as 0 during frame trans-

mission, a packet transmission

which is incomplete will have a

guaranteed

CRC

violation

appended before the internal

Transmit FIFO is cleared. No

subsequent attempts to load the

FIFO should be made until

ENXMT is set and TDTREQ is

asserted. ENXMT is cleared by

activation of the RESET pin or

SWRST bit.

Bit 0

ENRCV

Enable Receive. Setting ENRCV

= 1 enables reception of frames.

With ENRCV = 0, no frames will

be received from the network

into the internal FIFO. When

ENRCV is written as 0, any

receive

frame

currently

progress will be completed (and

valid

data

contained

the

RCVFIFO can be read by the

host) and the MACE device will

enter the monitoring state for

missed

packets.

Note

that

clearing the ENRCV bit disables

the assertion of RDTREQ. If

ENRCV is cleared during re-

ceive

activity

and

remains

cleared for a long time and if the

tail end of the receive frame cur-

rently in progress is longer than

the amount of space available in

the

Receive

FIFO,

Receive

FIFO overflow will occur. How-

ever, even with RDTREQ deas-

serted, if there is valid data in the

Receive FIFO to be read, suc-

cessful

slave

reads

the

Receive FIFO can be executed

(indicated by valid DTV). It is the

host’s responsibility to avoid the

overflow situation. ENRCV is

cleared by activation of the

RESET pin or SWRST bit.

PLS Configuration

Control (PLSCC)

(REG ADDR 14)

All bits within the PLS Configuration Control register

are cleared upon a hardware or software reset. Bit

assignments are as follows:

Bit

Name

Description

Bit 7-4

RES

Reserved.

Read

zeroes.

Always write as zeroes.

Bit 3

XMTSEL

Transmit Mode Select. XMTSEL

provides control over the AUI

DO+ and DO– operation while

the MACE device is not transmit-

ting. With XMTSEL = 0, DO+

and DO will be equal during

transmit idle state, providing

zero differential to operate trans-

former coupled loads. The turn

off and return to zero delays are

controlled

internally.

With

XMTSEL = 1, DO+ is positive

with respect to DO during the

transmit idle state .

Bit 2-1

PORTSEL

Port Select. PORTSEL is used

[1-0]

select

between

the

AUI,

10BASE–T, DAI or GPSI ports

of the MACE device. PORTSEL

is cleared by hardware or soft-

ware reset. PORTSEL will deter-

mine which of the interfaces is

used during normal operation, or

tested when utilizing the loop-

back options (LOOP [1-0]) in the

User Test Register. Note that

the PORTSEL [1–0] program-

ming will be overridden if the

ASEL bit in the PHY Configura-

tion Control register is set.

RES

XMTSEL

PORTSEL [1-0]

ENPLSIO

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