AM79C940KCSLASHW datasheet(53/144 Pages) AMD

53 / 144 page

Am79C940

the host memory, the host is responsible for ensuring

that the tail end of the frame does not get written into

the FIFO and does not get transmitted as a whole

frame. It is recommended that the host clear the tail

end of the frame from the host memory before request-

ing the XMT FS re ad so th at after the XMTFS

read,when the MACE device re-asserts TDTREQ, the

tail end of the frame does not get written into the FIFO.

The Transmit Frame Status read will indicate that the

LCOL error occurred. The read operation on the Trans-

mit Frame Status will update the FIFO read and write

pointers. If no End-of-Frame write (EOF pin assertion)

had occurred during the FIFO write sequence, the en-

tire transmit path will be reset (which will update the

Transmit FIFO watermark with the current XMTFW

value in the FIFO Configuration Control register). If a

whole frame resides in the FIFO, the read pointer will

be moved to the start of the next frame or free location

in the FIFO, and the write pointer will be unaffected.

TDTREQ will not be re-asserted until the Transmit

Frame Status has been read.

After an LCOL error, all further packet transmission will

be suspended until the Transmit Frame Status is read,

regardless of whether additional packet data exists in

the FIFO to be transmitted. Receive FIFO operations

are unaffected.

Packets experiencing a late collision will not be re-tried.

Recovery from this condition must be performed by

upper layer software.

pletion of a transmitted message, the AUI CI

± pair is

asserted by some transceivers as a self-test. When the

AUI port has been selected, the integral Manchester

Encoder/Decoder will expect the SQE Test Message

(nominal 10 MHz sequence) to be returned via the CI

pair, within a 40 network bit time period after DI

± goes

inactive. If the CI

± input is not asserted within the 40

network bit time period following the completion of

transmission, then the MACE device will set the CERR

bit (bit 5) in the Interrupt Register. The INTR pin will be

activated if the corresponding mask bit CERRM = 0.

When the GPSI port is selected, the MACE device will

expect the CLSN input pin to be asserted 40 bit times

after the transmission has completed (after TXEN out-

put pin has gone inactive). When the DAI port has

been selected, the CERR bit will not be reported. A

transceiver connected via the DAI port is not expected

to support the SQE Test Message feature.

Host related transmit exception conditions include:

(a) Overflow caused by excessive writes to the

Transmit FIFO (DTV will not be issued if the Trans-

mit FIFO is full).

(b) Underflow caused by lack of host writes to the

Transmit FIFO.

(a) The host may continue to write to the Transmit FIFO

after the TDTREQ has been de-asserted, and can

safely do so on the basis of knowledge of the number

of free bytes remaining (set by XMTFW in the FIFO

Configuration Control register). If however the host

system continues to write data to the point that no ad-

ditional FIFO space exists, the MACE device will not

return the DTV signal and hence will effectively not

acknowledge acceptance of the data. It is the host’s

responsibility to ensure that the data is re-presented at

a future time when space exists in the Transmit FIFO,

and to track the actual data written into the FIFO.

(b) If the host fails to respond to the TDTREQ from the

MACE device before the Transmit FIFO is emptied, a

FIFO underrun will occur. The MACE device will in this

case terminate the network transmission in an orderly

sequence. If less than 512 bits have been transmitted

onto the network the transmission will be terminated

immediately, generating a runt packet. If greater than

512 bits have been transmitted, the message will have

the current CRC inverted and appended at the next

byte boundary, to guarantee an FCS error is detected

at the receiving station. The MACE device will report

this condition to the host by de-asserting the TDTREQ

pin, setting the UFLO and XMTSV bits (in the Transmit

Frame Status) and the XMTINT bit (in the Interrupt

responding XMTINTM bit (in the Interrupt Mask

Regis ter) is cleared.

Once the XMTINT condition has been externally recog-

nized, the Transmit Frame Counter (XMTFC) can be

read to determine whether the tail end of the frame that

suffers the UFLO error is still in the host memory (i.e.,

when XMTFC = 0). In the case of FIFO underrun, this

will definitely be the case and the host is responsible for

ensuring that the tail end of the frame does not get writ-

ten into the FIFO and does not get transmitted as a

whole frame. It is recommended that the host clear the

tail end of the frame from the host memory before

requesting the XMTFS read so that after the XMTFS

read, when the MACE device re-asserts TDTREQ, the

tail end of the frame does not get written into the FIFO.

The Transmit Frame Status read will indicate that the

UFLO error occurred. The read operation on the Trans-

mit Frame Status will update the FIFO read and write

pointers and the entire transmit path will be reset

(which will update the Transmit FIFO watermark with

the current XMTFW value in the FIFO Configuration

Control register). TDTREQ will not be re-asserted until

the Transmit Frame Status has been read.

Frame Status for up to two packets. If the host fails to

read the Transmit Frame Status and both internal

entries become occupied, the MACE device will not

commence any subsequent transmit frames to prevent

overwriting of the internally stored values. This will

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