AM79C940KCSLASHW datasheet(57/144 Pages) AMD

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Am79C940

will eventually cause an overflow condition. The FIFO

will maintain any previously completed packet(s), which

can be read by the host at its convenience. However,

packet data on the network will no longer be received,

regardless of destination address, until the overflow is

cleared by reading the remaining Receive FIFO data

and Receive Status. The MACE device will increment

the Missed Packet Count (MPC) register to indicate that

a packet which would have been normally passed to the

host, was dropped due to the error condition.

Note: The moment a packet overflow is detected or

read, an EOF with INT is generated. On status read

(OFLOW), the FIFO pointers are reset to the first

location. This essentially flushes the FIFO.

LOOPBACK OPERATION

During loopback, the FCS logic can be allocated to the

receiver by setting RCVFCSE = 1 in User Test Regis-

ter. This permits both the transmit and receive FCS op-

erations to be verified during the loopback process.

The state of RCVFCSE is only valid during loopback

opera tion.

If RCVFCSE = 0, the MACE device will calculate and

append the FCS to the transmitted message. The

receive message passed to the host will therefore con-

tain an additional four bytes of FCS. The Receive

Frame Status will indicate the result of the loopback

operation and the RCVCNT.

If RCVFCSE = 1, the last four bytes of the transmit

message must contain the FCS computed for the

transmit data preceding it. The MACE device will trans-

mit the data without addition of an FCS field, and the

FCS will be calculated and verified at the receiver.

The loopback facilities of the MACE device allow full

operation to be verified without disturbance to the net-

work. Loopback operation is also affected by the state

of the Loopback Control bits (LOOP [0–1]) in the User

Test Register. This affects whether the internal MEN-

DEC is considered part of the internal or external

loop-back path.

When in the loopback mode(s), the multicast address

detection feature of the MACE device, programmed by

the contents of the Logical Address Filter (LADR [63–

0]) can only be tested when RCVFCSE = 1, allocating

the CRC generator to the receiver. All other features

operate identically in loopback as in normal operation,

such as automatic transmit padding and receivepad

stripping.

USER ACCESSIBLE REGISTERS

The following registers are provided for operation of the

MACE device. All registers are 8-bits wide unless

otherwise stated. Note that all reserved register bits

should be written as zero.

Receive FIFO (RCVFIFO)

(REG ADDR 0)

This register provides a 16-bit data path from the

Receive FIFO. Reading this register will read one word/

byte from the Receive FIFO. The RCVFIFO should

only be read when Receive Data Transfer Request

(RDTREQ) is asserted. If the RCVFIFO location is read

before 64-bytes are available in the RCVFIFO (or

12-bytes in the case that LLRCV is set in the Receive

Frame Control register), DTV will not be returned.

Once the 64-byte threshold has been achieved and

RDTREQ is asserted, the de-assertion of RDTREQ

does not prevent additional data from being read from

the RCVFIFO, but indicates the number of additional

bytes which are present, before the RCVFIFO is emp-

tied, and subsequent reads will not return DTV (see

the FIFO Sub-System section for additional details).

Write operations to this register will be ignored and

DTV will not be returned.

Byte transfers from the RCVFIFO are supported, and

will be fully aligned to the target memory architecture,

defined by the BSWP bit in the BIU Configuration Con-

trol register. The Byte Enable inputs (BE1-0) will define

which half of the data bus should be used for the trans-

fer. The external host/controller will be informed that

the last byte/word of data in a receive frame is being

read from the RCVFIFO, when the MACE device as-

serts the EOF signal.

Transmit FIFO (XMTFIFO)

(REG ADDR 1)

This register provides a 16-bit data path to the Transmit

FIFO. Byte/word data written to this register will be

placed in the Transmit FIFO. The XMTFIFO can be

written at any time the Transmit Data Transfer Request

(TDTREQ) is asserted. The de-assertion of TDTREQ

does not prevent data being written to the XMTFIFO,

but indicates the number of additional write cycles

which can take place, before the XMTFIFO is filled, and

subsequent writes will not return DTV (see the FIFO

Sub-System section for additional details). Read oper-

ations to this register will be ignored and DTV will not

be returned.

Byte transfers to the XMTFIFO are supported, and

accept data from the source memory architecture to

ensure the correct byte ordering for transmission,

defined by the BSWP bit in the MAC Configuration

Control register. The Byte Enable inputs (BE1-0) will

define which half of the data bus should be used for the

transfer. The use of byte transfers have implications on

the latency time provided by the XMTFIFO (see the

FIFO Sub-System section for additional details). The

external host/controller must indicate the last byte/word

RCVFIFO [15–0]

XMTFIFO [15–0]

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