AM79C940KCSLASHW datasheet(40/144 Pages) AMD

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Am79C940

Input Signal Conditioning

Transient noise pulses at the input data stream

are rejected by the Noise Rejection Filter. Pulse width

rejection is proportional to transmit data rate. DC

inputs more negative than minus 100 mV ar e

also suppressed.

The Carrier Detection circuitry detects the presence of

an incoming data packet by discerning and rejecting

noise from expected Manchester data, and controls the

stop and start of the phase-lock loop during clock

acq uisition. Clock acquisition requ ire s a valid

Manchester bit pattern of 1010 to lock onto the

incoming message.

When input amplitude and pulse width conditions are

met at DI

±, the internal enable signal from the SIA to

controller (RXCRS) is asserted and a clock acquisition

cycle is initiated.

Clock Acquisition

When there is no activity at DI

± (receiver is idle), the

receive oscillator is phase locked to TCK. The first neg-

ative clock transition (bit cell center of first valid

Manchester “0") after RXCRS is asserted interrupts the

receive oscillator. The oscillator is then restarted at the

second Manchester “0" (bit time 4) and is phase locked

to it. As a result, the SIA acquires the clock from the

incoming Manchester bit pattern in 4 bit times with a

“1010" Manchester bit pattern.

SRDCLK and SRD are enabled 1/4 bit time after clock

acquisition in bit cell 5 if the ENPLSIO bit is set in the

PLS configuration control register. SRD is at a HIGH

state when the receiver is idle (no SRDCLK). SRD

however, is undefined when clock is acquired and may

remain HIGH or change to LOW state whenever

SRDCLK is enabled. At 1/4 bit time through bit cell 5,

the controller portion of the MACE device sees the first

SRDCLK transition. This also strobes in the incoming

fifth bit to the SIA as Manchester “1". SRD may make a

transition after the SRDCLK rising edge bit cell 5, but

its state is still undefined. The Manchester “1" at bit 5 is

clocked to SRD output at 1/4 bit time in bit cell 6.

PLL Tracking

After clock acquisition, the phase-locked clock is com-

pared to the incoming transition at the bit cell center

(BCC) and the resulting phase error is applied to a

correction circuit. This circuit ensures that the

phase-locked clock remains locked on the received

signal. Individual bit cell phase corrections of the Volt-

age Controlled Oscillator (VCO) are limited to 10%

of the phase differencebetween BCCand phase-

locked clock.

Carrier Tracking and End of Message

The carrier detection circuit monitors the DI

± inputs

after RXCRS is asserted for an end of message.

RXCRS de-asserts 1 to 2 bit times after the last positive

transition on the incoming message. This initiates the

end of reception cycle. The time delay from the last ris-

ing edge of the message to RXCRS deassert allows

the last bit to be strobed by SRDCLK and transferred to

the controller section, but prevents any extra bit(s) at

the end of message. When IRENA de-asserts (see

Receive Timing-End of Reception (Last Bit = 0) and

Receive Timing-End of Reception (Last Bit = 1) wave-

form diagrams) an RXCRS hold off timer inhibits

RXCRS assertion for at least 2 bit times.

Data Decoding

The data receiver is a comparator with clocked output

to minimize noise sensitivity to the DI

± inputs. Input

error is less than

± 35 mV to minimize sensitivity to

Data

Receiver

Manchester

Decoder

Noise

Reject

Filter

Carrier

Detect

Circuit

SRD

SRDCLK

RXCRS

16235D-5

Receiver Block Diagram

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