AM79C940KCSLASHW datasheet(46/144 Pages) AMD

46 / 144 page

Am79C940

available. EAR must have a pulse width of at least

200 ns.

Note that setting the PROM bit (MAC Configuration

Control) will cause all receive packets to be received,

regardless of the programming of M/R or the state of

the EAM/R input. The following table summarizes the

operation of the EADI features.

Internal/External Address Recognition Capabilities

General Purpose Serial Interface (GPSI)

The GPSI port provides the signals necessary to

present an interface consistent with the non encoded

data functions observed to/from a LAN controller such

as the Am7990 Local Area Network Controller for

Ethernet (LANCE). The actual GPSI pins are function-

ally identical to some of the pins from the DAI and the

EADI ports, the GPSI replicates this type of interface.

The GPSI allows use of an external Manchester

encoder/decoder, such as the Am7992B Serial Inter-

face Adapter (SIA). In addition, it allows the MACE

device to be used as a MAC sublayer engine in a

repeater based on the Am79C980 Integrated Multiport

Repeater (IMR). Simple connection to the IMR Expan-

sion Bus allows the MAC to view all packet data pass-

ing through a number of interconnected IMRs, allowing

statistics and network management information to

be collected.

The GPSI functional pins are duplicated as follows:

Pin Configuration for GPSI Function

IEEE 1149.1 Test Access Port Interface

An IEEE 1149.1 compatible boundary scan Test

Access Port is provided for board level continuity test

and diagnostics. All digital input, output and input/out-

put and input/output pins are tested. Analog pins,

including the AUI differential driver (DO

±) and receiv-

ers DI

±, CI±), and the crystal input (XTAL1/XTAL2)

pins, are not tested.

The following is a brief summary of the IEEE 1149.1

compatible test functions implemented in the MACE

device. For additional details, consult the IEEE Stan-

dard Test Access Port and Boundary-Scan Architec-

ture document (IEEE Std 1149.1–1990).

The boundary scan test circuit requires four pins (TCK,

TMS, TDI and TDO ), defined as the Test Access Port

(TAP). It includes a finite state machine (FSM), an

instruction register, a data register array and a power

on reset circuit. Internal pull-up resistors are provided

for the TCK, TDI and TMS pins.

The TAP engine is a 16 state FSM, driven by the Test

Clock (TCK) and the Test Mode Select (TMS) pins. An

independent power on reset circuit is provided to

ensure the FSM is in the TEST_LOGIC_RESET state

at power up.

In addition to the minimum IEEE 1149.1 instruction

requirements (EXTEST, SAMPLE and BYPASS), three

additional instructions (IDCODE, TRI_ST and SET_I/

O) are provided to further ease board level testing. All

unused instruction codes are reserved.

IEEE 1149.1 Supported Instruction Summary

PROM

M/R

EAM/R

Required Timing

Received Messages

No timing requirements

All Received Frames

No timing requirements

All Received Frames

↓

Low for 200 ns within 512-bits after SFD

Physical/Logical/Broadcast Matches

No timing requirements

Physical/Logical/Broadcast Matches

↓

Low for 200 ns within 8-bits after DA field

All Received Frames

Function

Type

LANCE

MACE

Receive Data

RXDAT

Receive Clock

RCLK

SRDCLK

Receive Carrier Sense

RENA

RXCRS

Collision

CLSN

Transmit Data

TXDAT+

Transmit Clock

TCK

STDCLK

Transmit Enable

TENA

TXEN

Inst

ame

Description

Selected

Data Reg

Reg

Mode

Inst

Code

EXTEST External Test

BSR

Test

0000

IDCode

ID Code Inspection

ID Reg

Normal

0001

Sample

Sample Boundary

BSR

Normal

0010

TRI_ST

Force Tristate

Bypass

Normal

0011

SET_I/0

Control

BoundaryTo I/0

Bypass

Test

0100

Bypass

Bypass Scan

Bypass

Normal

1111

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