AM79C940KCSLASHW datasheet(54/144 Pages) AMD

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Am79C940

occur regardless of the number of bytes written to the

Transmit FIFO.

RECEIVE OPERATION

The receive operation and features of the MACE de-

vice are controlled by programmable options. These

options are programmed through the BIU, FIFO and

MAC Configuration Control registers.

Parameters controlled by the MAC Configuration Con-

trol register are generally programmed only once, dur-

ing initialization, and are therefore static during the

normal operation of the MACE device (see the Media

Access Control section for a detailed description). The

features controlled by the FIFO Configuration Control

programmed without performing a reset on the part.

The host is responsible for ensuring that no data is

present in the Receive FIFO when re-programming the

receive attributes.

Receive FIFO Read

The Receive FIFO is accessed by performing a host

generated read sequence on the MACE device. See

the Slave Access Operation-Read Access section and

the AC Waveforms section, Host System Interface, fig-

ures: “2 Cycle Receive FIFO/Register Read Timing”

and “3 Cycle Receive FIFO/Register Read Timing” for

details of the read access timing.

Note that EOF will be asserted by the MACE device

during the last data byte/word transfer.

Receive Function Programming

The Receive Frame Control register allows program-

ming of the automatic pad field stripping feature and

the configuration of the Match/Reject (M/R) pin.

ASTRP RCV and M/R must be static when the receive

function is enabled (ENRCV = 1). The receiver should

be disabled before (re-) programming these options.

The EADI port can be used to permit reception of

frames to commence whilst external address decoding

takes place. The M/R bit defines the function of the

EAM/R pin, and hence whether frames will be

accepted or re jected by the exte rnal address

comparison logic.

The programming of additional receive attributes are

distributed between the FIFO and MAC Configuration

Control registers, and the User Test Register.

All receive frames can be accepted by setting the

PROM bit (bit 7) in the MAC Configuration Control reg-

ister. When PROM is set, the MACE device will attempt

to receive all messages, subject to minimum frame

enforcement. Setting PROM will override the use of the

EADI port to force the rejection of unwanted messages.

See the sections External Address Detection Interface

for more details.

The point at which RDTREQ is asserted in relation to

the number of bytes of a frame that are present in the

Receive FIFO (RCVFIFO) is controlled by the RCVFW

bits in the FIFO Configuration Control register, or the

LLRCV bit in the Receive Frame Control register.

RDTREQ will be asserted when one of the following

conditions is true:

(i)

There are at least 64 bytes in the RCVFIFO.

(ii) The received packet has passed the 64 byte mini-

mum criteria, and the number of bytes in the

RCVFIFO is greater than or equal to the threshold

set by the RCVFW (16 or 32 bytes).

(iii) A receive packet has completed, and part or all of

it is present in the RCVFIFO.

(iv) The LLRCV bit has been set and greater than

12-bytes of at least 8 bytes have been received.

Note that if the RCVFW is set below the 64-byte limit,

the MACE device will still require 64-bytes of data to be

received before the initial assertion of RDTREQ. Sub-

sequently, RDTREQ will be asserted at any time the

RCVFW threshold is exceeded. The only times that the

RDTREQ will be asserted when there are not at least

an initial 64-bytes of data in the RCVFIFO are:

(i) When the ASTRP RCV bit has been set in the Re-

ceive Frame Control register, and the pad is auto-

matically stripped from a minimum length packet.

(ii) When the RPA bit has been set in the User Test

been received.

(iii) When the LLRCV bit has been set in the Receive

Frame Control register, and at least 12-bytes (after

SFD) has been received.

No preamble/SFD bytes are loaded into the Receive

FIFO. All references to bytes past through the receive

FIFO are received after the preamble/SFD sequence.

Depending on the bus latency of the system, RCVFW

can be set to ensure that the RCVFIFO does not over-

flow before more data is read. When the entire frame is

in the RCVFIFO, RDTREQ will be asserted regardless

of the value in RCVFW. The default value of RCVFW is

64-bytes after hardware or software reset.

The receive operation of the MACE device can be

halted at any time by clearing the ENRCV bit in the

MAC Configuration Control register. Note that any

receive frame currently in progress will be accepted

normally, and the MACE device will disable the receive

process once the message has completed. The Missed

Packet Count (MPC) will be incremented for

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