AM79C940KCSLASHW datasheet(60/144 Pages) AMD

60 / 144 page

Am79C940

tional data once a packet is in

progress will not cause the

RCVFIFO to underflow, and will

be indicated

by DTV being

invalid. The MACE device will no

longer be able to reject runts in

this mode, this responsibility is

transferred to the host system.

In the case of a collided packet

(normal slot time collision or late

collision), the MACE device will

abort the reception, and return

the RCVFS. Note that all colli-

sions in this mode will appear as

late collisions and be reported

by the CLSN bit in the Receive

Status (RCVSTS) byte.

If the host does not keep up with

the incoming receive data, nor-

mal RCVFIFO overflow recovery

is provided.

Bit 2

M/R

Match/Reject. The Match/Reject

option sets the criteria for the

External

Address

Detection

Interface. If set, the EAM/R pin is

configured as External Address

Match, and is used to signal the

acceptance of a receive frame to

the MACE device. If cleared, the

functions

External

Address Reject and is used to

flush unwanted packets from the

Receive FIFO prior to the first

assertion of RDTREQ. M/R is

cleared by activation of the

RESET pin or SWRST bit. When

the EADI feature is disabled, the

EAM/R pin must be tied active

(low) and all normal receive ad-

dress recognition configurations

are supported (physical, logical

and promiscuous). See the sec-

tion “External Address Detection

Interface” for additional details.

Bit 1

RES

Reserved. Read as zero. Always

write as zero. Bit 0 ASTRP RCV

Auto

Strip

Receive.

ASTRP

RCV enables the automatic pad

stripping feature. The pad and

FCS fields will be stripped from

receive frames and not placed in

the FIFO. ASTRP RCV is set by

activation of the RESET pin or

the SWRST bit.

Receive Frame Status (RCVFS)

(REG ADDR 6)

The Receive Frame Status is a single byte location

which must be read by four read cycles to obtain the

four bytes (32-bits) of status associated with each

receive frame. Receive Frame Status can be read

using either the Register Direct or FIFO Direct access

modes.

In Register Direct mode, access to the Receive FIFO

will be denied until all four status bytes for the com-

pleted frame have been read from the Receive Frame

Status location. In FIFO Direct mode, the Receive

Frame Status is read through the Receive FIFO loca-

tion, by continuing to execute four read cycles after the

completion of packet data (and assertion of EOF). The

Receive Frame Status can be read using either mode,

or a combination of both modes, however each status

byte will be presented only once regardless of access

method. Other register reads and/or writes can be

interleaved at any time, during the Receive Frame

Sta tus sequence.

The Receive Frame Status consists of the following

four bytes of information:

RFS0

Receive Message Byte Count

(RCVCNT) [11–0]

RFS1

Receive Status, (RCVSTS) [15–12]

RFS2

Runt Packet Count (RNTPC) [7–0]

RFS3

Receive Collision Count (RCVCC) [7–0]

RFS0—Receive Message Byte Count (RCVCNT)

Bit

Name

Description

Bit 7-0

RCVCNT

The

Receive

Message Byte

[7:0]

Count indicates the number of

whole bytes in the received mes-

sage. If pad bytes were stripped

from

the

received

frame,

RCVCNT indicates the number

of bytes received less the num-

ber of pad bytes and less the

number of FCS bytes. RCVCNT

is 12 bits long. If a late collision

detected

(CLSN

set

RCVSTS), the count is an indi-

cation of the length (in byte

times) of the duration of the re-

ceive activity including the colli-

sion.

RCVCNT

[10:8]

corre-

spond to bits 3-0 in RFS1 of the

Receive

Frame

Status.

RCVCNT [11–0] will be invalid

when OFLO is set.

RFS1—Receive Status (RCVSTS)

Bit

Name

Description

Bit 7

OFLO

Overflow flag. Indicates that the

Receive FIFO over flowed due

RCVFS [31–00]

OFLO CLSN FRAM FCS

RCVCNT [10:8]

RCVCNT [7:0]

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