AM79C940KCSLASHW datasheet(64/144 Pages) AMD

64 / 144 page

Am79C940

the MACE device regardless of

the state of the RCVCCO bit, if

RCVCCOM is set. It is cleared

by activation of the RESET pin

or SWRST bit.

Bit 3

RNTPCOM Runt Packet Count Overflow

Mask. RNTPCOM is the mask

for

RNTPCO

(Runt

Packet

Count Overflow). The INTR pin

will not be asserted by the

MACE device regardless of the

state of the RNTPCO bit, if

RNTPCOM is set. It is cleared by

activation of the RESET pin or

SWRST bit.

Bit 2

MPCOM

Missed Packet Count Overflow

Mask. MPCOM is the mask for

MPCO (Missed Packet Count

Overflow). The INTR pin will not

be asserted by the MACE device

regardless of the state of the

MPCO bit, if MPCOM is set. It is

cleared by activation of the

RESET pin or SWRST bit.

Bit 1

RCVINTM

Receive

Interrupt

Mask.

RCVINTM

the

mask

for

RCVINT. The INTR pin will not

be asserted by the MACE device

regardless of the state of the

RCVINT bit, if RCVINTM is set. It

is cleared by activation of the

RESET pin or SWRST bit.

Bit 0

XMTINTM

Transmit

Interrupt

Mask.

XMTINTM

the

mask

for

XMTINT. The INTR pin will not

be asserted by the MACE device

regardless of the state of the

XMTINT bit, if XMTINT is set. It

is cleared by activation of the

RESET pin or SWRST bit

Poll Register (PR)

(REG ADDR 10)

This register contains copies of internal status bits to

simplify a host implementation which is non-interrupt

driven. The register is read only, and its status is unaf-

fected by read operations. All register bits are cleared

by hardware or software reset. Bit assignments are as

follows:

Bit

Name

Description

Bit 7

XMTSV

Transmit Status Valid. Transmit

Status Valid indicates that the

Transmit Frame Status is valid.

Bit 6

TDTREQ

Transmit

Data

Transfer

Request. An internal indication

of the current request status of

the Transmit FIFO. TDTREQ is

set when the external TDTREQ

signal is asserted.

Bit 5

RDTREQ

Receive Data Transfer Request.

An internal indication of the cur-

rent

request

status

the

Receive FIFO. RDTREQ is set

when the external RDTREQ

signal is asserted.

Bit 4-0

RES

Reserved.

Read

zeroes.

Always write as zeroes.

BIUConfigurationControl(BIUCC)

(REGADDR11)

All bits within the BIU Configuration Control register will

be set to their default state upon a hardware or soft-

ware reset. Bit assignments are as follows:

Bit

Name

Description

Bit 7

RES

Reserved. Read as zero. Always

write as zero.

Bit 6

BSWP

Byte Swap. The BSWP function

allows data to and from the

FIFOs to be orientated accord-

ing to little endian or big endian

byte

ordering

conventions.

BSWP is cleared by by activa-

tion of the RESET pin or SWRST

bit,

defaulting

Intel

byte

ordering.

Bit 5-4

XMTSP

Transmit Start Point. XMTSP

[1-0]

controls

the

point

preamble

transmission

commences

relation to the number of bytes

written to the XMTFIFO. When

the entire frame is in the XMT-

FIFO (or the XMTFIFO becomes

full

before

the

threshold

achieved), transmission of pre-

amble will start regardless of the

value in XMTSP (once the IPG

time has expired). XMTSP is

given a value of 10 (64 bytes)

after hardware or software reset.

Regardless of XMTSP, the FIFO

will not internally over write its

data until at least 64 bytes, or the

entire frame, has been transmit-

ted

onto

the

network.

This

ensures that for collisions within

the slot time window, transmit

data need not be re-written to

the XMTFIFO, and re-tries will

be handled autonomously by the

MACE device.

XMTSV

TDTREQ

RDTREQ

RES

BSWP XMTSP [1-0]

RES

SWRST

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