AM79C940KCSLASHW datasheet(27/144 Pages) AMD

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Am79C940

Chip Select (Input)

Used to access the MACE device FIFOs and internal

registers locations using the ADD address bus. The

FIFOs may alternatively be directly accessed without

supplying the FIFO address, by using the FDS and

R/W pins.

INTR

Interrupt (Output, Open Drain)

An attention signal indicating that one or more of the

following status flags are set: XMTINT, RCVINT,

MPCO, RPCO, RCVCCO, CERR, BABL, or JAB. Each

interrupt source can be individually masked. No inter-

rupt condition can take place in the MACE device

immediately after a hardware or software reset.

RESET

Reset (Input)

Reset clears the internal logic. Reset can be asynchro-

nous to SCLK, but must be asserted for a minimum

duration of 15 SCLK cycles.

SCLK

System Clock (Input)

The system clock input controls the operational fre-

quency of the slave interface to the MACE device and

the internal processing of frames. SCLK is unrelated to

the 20 MHz clock frequency required for the 802.3/

Ethernet interface. The SCLK frequency range is

1 MHz-25 MHz.

EDSEL

System Clock Edge Select (Input)

EDSEL is a static input that allows System Clock

(SCLK) edge selection. If EDSEL is tied high, the bus

interface unit will assume falling edge timing. If EDSEL

is tied low, the bus interface unit will assume rising

edge timing, which will effectively invert the SCLK as it

enters the MACE device, i.e., the address, control lines

(CS, R/W, FDS, etc) and data are all latched on the ris-

ing edge of SCLK, and data out is driven off the rising

edge of SCLK.

Timing Control (Input)

The Timing Control input conditions the minimum num-

ber of System Clocks (SCLK) cycles taken to read or

write the internal registers and FIFOs. TC can be used

as a wait state generator, to allow additional time for

data to be presented by the host during a write cycle,

or allow additional time for the data to be latched during

a read cycle. TC has an internal (SLEEP disabled)

pull up.

Timing Control

IEEE 1149.1 TEST ACCESS PORT (TAP)

INTERFACE

TCK

Test Clock (Input)

The clock input for the boundary scan test mode oper-

ation. TCK can operate up to 10 MHz. TCK has an in-

ternal (not SLEEP disabled) pull up.

TMS

Test Mode Select (Input)

A serial input bit stream used to define the specific

boundary scan test to be executed. TMS has an inter-

nal (not SLEEP disabled) pull up.

TDI

Test Data Input (Input)

The test data input path to the MACE device. TDI has

an internal (not SLEEP disabled) pull up.

TDO

Test Data Out (Output)

The test data output path from the MACE device.

GENERAL INTERFACE

XTAL1

Crystal Connection (Input)

The internal clock generator uses a 20 MHz crystal that

is attached to pins XTAL1 and XTAL2. Internally, the

20 MHz crystal frequency is divided by two which

determines the network data rate. Alternatively, an

external 20 MHz CMOS-compatible clock signal can be

used to drive this pin. The MACE device supports the

use of 50 pF crystals to generate a 20 MHz frequency

which is compatible with the IEEE 802.3 network

fre quency tolerance and jitter specifications.

XTAL2

Crystal Connection (Output)

The internal clock generator uses a 20 MHz crystal that

is attached to pins XTAL1 and XTAL2. If an external

clock generator is used on XTAL1, then XTAL2 should

be left unconnected.

SLEEP

Sleep Mode (Input)

The optimal power savings made is extracted by

asserting the SLEEP pin with both the Auto Wake

(AWAKE bit) and Remote Wake (RWAKE bit) functions

disabled. In this “deep sleep” mode, all outputs will be

forced into their inactive or high impedance state, and

all inputs will be ignored except for the SLEEP, RESET,

SCLK, TCK, TMS, and TDI pins. SCLK must run for 5

cycles after the assertion of SLEEP. During the “Deep

Sleep”, the SCLK input can be optionally suspended

for maximum power savings. Upon exiting “Deep

Sleep”, the hardware RESET pin must be asserted and

the SCLK restored. The system must delay the setting

Number of

Clocks

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