M68HC05 datasheet(57/118 Pages) FREESCALE

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Timer During Wait Mode

MC68HC05C9A Advance Information Data Sheet, Rev. 4.1

Freescale Semiconductor

To prevent OCF from being set between the time it is read and the time the output compare registers are

updated, use this procedure:

Disable interrupts by setting the I bit in the condition code register.

Write to OCRH. Compares are now inhibited until OCRL is written.

Clear bit OCF by reading timer status register (TSR).

Enable the output compare function by writing to OCRL.

Enable interrupts by clearing the I bit in the condition code register.

8.4 Timer During Wait Mode

The CPU clock halts during the wait mode, but the timer remains active. If interrupts are enabled, a timer

interrupt will cause the processor to exit the wait mode.

8.5 Timer During Stop Mode

In the stop mode, the timer stops counting and holds the last count value if STOP is exited by an interrupt.

If STOP is exited by reset, the counters are forced to $FFFC. During STOP, if at least one valid input

capture edge occurs at the TCAP pins, the input capture detect circuit is armed. This does not set any

timer flags or wake up the MCU, but if an interrupt is used to exit stop mode, there is an active input

capture flag and data from the first valid edge that occurred during the stop mode. If reset is used to exit

stop mode, then no input capture flag or data remains, even if a valid input capture edge occurred.

M68HC05 bảng dữ liệu(PDF) 57 Page - Freescale Semiconductor, Inc