M68HC05 datasheet(43/118 Pages) FREESCALE

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MC68HC05C12A Compatible COP Clear Register

MC68HC05C9A Advance Information Data Sheet, Rev. 4.1

Freescale Semiconductor

5.7 MC68HC05C12A Compatible COP Clear Register

The COP clear register, shown in Figure 5-6, resets the C12A COP counter.

COPC — Computer Operating Properly Clear Bit

Preventing a COP reset is achieved by writing a 0 to the COPC bit. This action will reset the counter

and begin the timeout period again. The COPC bit is bit 0 of address $3FF0. A read of address $3FF0

will result in the data programmed into the mask option register PBMOR.

5.8 COP During Wait Mode

Either COP will continue to operate normally during wait mode. The software must pull the device out of

wait mode periodically and reset the COP to prevent a system reset.

5.9 COP During Stop Mode

Stop mode disables the oscillator circuit and thereby turns the clock off for the entire device. The COP

counter will be reset when stop mode is entered. If a reset is used to exit stop mode, the COP counter will

be reset after the 4064 cycles of delay after stop mode. If an IRQ is used to exit stop mode, the COP

counter will not be reset after the 4064-cycle delay and will have that many cycles already counted when

control is returned to the program.

In the event that an inadvertent STOP instruction is executed, neither COP will allow the system to

recover. The MC68HC705C9A offers two solutions to this problem, one available in C9A mode (see 5.9.1

Clock Monitor Reset) and one available in C12A mode (see 5.9.2 STOP Instruction Disable Option).

5.9.1 Clock Monitor Reset

When configured as a C9A, the clock monitor circuit can provide a system reset if the clock stops for any

reason, including stop mode. When the CME bit in the C9A COP control register is set, the clock monitor

detects the absence of the internal bus clock for a certain period of time. The timeout period is dependent

on the processing parameters and varies from 5

µs to 100 µs, which implies that systems using a bus

clock rate of 200 kHz or less should not use the clock monitor.

If a slow or absent clock is detected, the clock monitor causes a system reset. The reset is issued to the

external system via the bidirectional RESET pin for four bus cycles if the clock is slow or until the clocks

recover in the case where the clocks are absent.

$3FF0

Bit 7

6543

Bit 0

Read:

Write:

COPC

Reset:

000

= Unimplemented

U = Undetermined

Figure 5-6. COP Clear Register (COPCLR)

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