M68HC05 datasheet(40/118 Pages) FREESCALE

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Resets

MC68HC05C9A Advance Information Data Sheet, Rev. 4.1

Freescale Semiconductor

Figure 5-2. Power-On Reset and RESET

5.4 Computer Operating Properly (COP) Reset

This device includes a watchdog COP feature which guards against program run-away failures. A timeout

of the computer operating properly (COP) timer generates a COP reset. The COP watchdog is a software

error detection system that automatically times out and resets the MCU if not cleared periodically by a

program sequence.

This device includes two COP types, one for C12A compatibility and the other for C9A compatibility. When

configured as a C9A the COP can be enabled by user software by setting COPE in the C9A COP control

programming the C12COPE bit in the C12A mask option register (C12MOR). The function and control of

both COPs is detailed below.

RESET

OSC1

INTERNAL

CLOCK

INTERNAL

ADDRESS

BUS

INTERNAL

DATA

BUS

NEW

PCH

NEW

PCL

CODe

CODE

PCH

PCL

CYC

4064t

CYC

VDDR

DUMMY

3FFF

NEW

3FFE

NEW

3FFE

3FFF

3FFE

DUMMY

Notes:

1. Internal timing signal and bus information are not available externally.

2. OSC1 line is not meant to represent frequency. It is only meant to represent time.

3. The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence.

RESET

(C9A)

(C12A)

4. RESET outputs VOL during 4064 power-on reset cycles when in C9A mode only.

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