M68HC05 datasheet(38/118 Pages) FREESCALE

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Interrupts

MC68HC05C9A Advance Information Data Sheet, Rev. 4.1

Freescale Semiconductor

4.4 Timer Interrupt

Three different timer interrupt flags cause a timer interrupt whenever they are set and enabled. The

interrupt flags are in the timer status register (TSR), and the enable bits are in the timer control register

(TCR). Any of these interrupts will vector to the same interrupt service routine, located at the address

specified by the contents of memory locations $3FF8 and $3FF9.

4.5 SCI Interrupt

Five different SCI interrupt flags cause an SCI interrupt whenever they are set and enabled. The interrupt

flags are in the SCI status register (SCSR), and the enable bits are in the SCI control register 2 (SCCR2).

Any of these interrupts will vector to the same interrupt service routine, located at the address specified

by the contents of memory locations $3FF6 and $3FF7.

4.6 SPI Interrupt

Two different SPI interrupt flags cause an SPI interrupt whenever they are set and enabled. The interrupt

flags are in the SPI status register (SPSR), and the enable bits are in the SPI control register (SPCR).

Either of these interrupts will vector to the same interrupt service routine, located at the address specified

by the contents of memory locations $3FF4 and $3FF5.

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