TMPR4925 datasheet(312/590 Pages) TOSHIBA

312 / 590 page

Chapter 10 PCI Controller

10-50

10.4.23 PCI Bus Arbiter Configuration Register (PBACFG)

0xD104

This register is only valid when using the on-chip PCI Bus Arbiter.

Reserved

: Type

: Initial value

321

Reserved

FIXPA RPBA PBAEN BMCEN

R/W

: Type

: Initial value

Bits

Mnemonic

Field Name

Description

31:4



Reserved



3FIXPA

Fixed Park

Master

Fixed Park Master (Initial value: 0, R/W)

Selects the method for determining the Park Master.

0: The last Bus Master becomes the Park Master.

1: Internal PCI Bus Arbiter Request Port A is the Park Master.

RPBA

Reset PCI Bus

Arbiter

Reset PCI Bus Arbiter (Initial value: 0, R/W)

Resets the PCI Bus Arbiter. However, the PCI Bus Arbiter Register settings are

saved. Please use the software to clear this bit.

1: The PCI Bus Arbiter is currently being reset.

0: The PCI Bus Arbiter is not currently being reset.

PBAEN

PCI Bus Arbiter

Enable

PCI Bus Arbiter Enable (Initial value: 0, R/W)

This is the Bus Arbiter Enable bit. After Reset, External PCI Bus requests to the PCI

Arbiter cannot be accepted until this bit is set to “1”. The PCI Controller is the default

Parking Master after Reset.

1: Enables the PCI Bus Arbiter.

0: Disables the PCI Bus Arbiter.

BMCEN

Broken Master

Check Enable

Broken Master Check Enable (Initial value: 0, R/W)

Controls Broken Master detection.

1: Enables the Broken PCI Bus Master check.

0: Disables the Broken PCI Bus Master check.

Figure 10.4.23 PCI Bus Arbiter Configuration Register

TMPR4925 bảng dữ liệu(PDF) 312 Page - Toshiba Semiconductor

TMPR4925 bảng dữ liệu(HTML) 312 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL